with while (i++ < MAX_CLOCK_ENABLE_WAIT); i can reach MAX_CLOCK_ENABLE_WAIT + 1
after the loop, so if (i == MAX_CLOCK_ENABLE_WAIT) that's still success.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Correspondence with the TI OMAP hardware team indicates that
SDRC_DLLA_CTRL.FIXEDDELAY should be initialized to 0x0f. This number
was apparently derived from process validation. This is only used
when the SDRC DLL is unlocked (e.g., SDRC clock frequency less than
83MHz).
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency. Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize. Without this delay, the system is prone to random
panics upon re-entering SDRAM.
This time delay varies based on MPU frequency. At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
On the OMAP3, initialize SDRC timings when the kernel boots. This ensures
that the kernel is running with known, optimized SDRC timings, rather than
whatever was configured by the bootloader.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The original CDP kernel that this code comes from waited for 0x800
loops after switching the CORE DPLL M2 divider. This does not appear
to be necessary.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This patch adds SMP platform specific parts for local(mpu) timer support
for OMAP4430 platform. Each Cortex-a9 core has it's own local timer in the
MPU domain. These timers are not in wakeup domain.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430
SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC
with GIC used for interrupt handling and SCU for cache coherency.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
This patch updates the Makefile and Kconfig entries for OMAP4. The OMAP4430 SDP
board file supports only minimal set of drivers.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds the support for OMAP4. The platform and machine specific
headers and sources updated for OMAP4430 SDP platform.
OMAP4430 is Texas Instrument's SOC based on ARM Cortex-A9 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for keypad, GPIO keys and LEDs. Also enable hardware
debounce feature for GPIO keys.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Setup regulators for MMC1 and MMC2 to get those SD slots
working again.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
CC: David Brownell <david-b@pacbell.net>
Acked-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Initialize regulators for Beagle and Overo.
Patch is based on earlier patches posted to linux-omap mailing
list.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Decouple the HSMMC glue from the twl4030 as the only
regulator provider, using the regulator framework instead.
This makes the glue's "mmc-twl4030" name become a complete
misnomer ... this code could probably all migrate into the
HSMMC driver now.
Tested on 3430SDP (SD and low-voltage MMC) and Beagle (SD),
plus some other boards (including Overo) after they were
converted to set up MMC regulators properly.
Eventually all boards should just associate a regulator with
each MMC controller they use. In some cases (Overo MMC2 and
Pandora MMC3, at least) that would be a fixed-voltage regulator
with no real software control. As a temporary hack (pending
regulator-next updates to make the "fixed.c" regulator become
usable) there's a new ocr_mask field for those boards.
Patch updated with a fix for disabling vcc_aux by
Adrian Hunter <adrian.hunter@nokia.com>
Cc: Pierre Ossman <drzeus-list@drzeus.cx>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Based on an earlier patches by Stanley.Miao <stanley.miao@windriver.com>
and Nishant Kamat <nskamat@ti.com>.
Note that at the ads7846 support still needs support for vaux_control
for the touchscreen to work.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Based on an earlier patch by Stanley.Miao <stanley.miao@windriver.com>
with board-*.c changes split to avoid conflicts with other device updates.
Cc: linux-fbdev-devel@lists.sourceforge.net
Signed-off-by: Stanley.Miao <stanley.miao@windriver.com>
Signed-off-by: Imre Deak <imre.deak@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add timing data for the Qimonda HYB18M512160AF-6 SDRAM chip, used on
the OMAP3430SDP boards.
Thanks to Rajendra Nayak <rnayak@ti.com> for his help identifying
the chip used on 3430SDP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add timing data for the Micron MT46H32M32LF-6 SDRAM chip, used on the
OMAP3 Beagle and EVM boards. Original timing data is from the Micron
datasheet PDF downloaded from:
http://download.micron.com/pdf/datasheets/dram/mobile/1gb_ddr_mobile_sdram_t48m.pdf
Thanks to Rajendra Nayak <rnayak@ti.com> for his help identifying
the chips used on Beagle & OMAP3EVM.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Move platform_device_register() for serial device to
omap_serial_init()
There is no need to have arch_initcall() dependency in serial
as already board files call the function omap_serial_init()
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Based on an earlier patch by Hunyue Yau <hyau@mvista.com> with
board-*.c changes split to avoid conflicts with other device updates.
Cc: linux-fbdev-devel@lists.sourceforge.net
Signed-off-by: Hunyue Yau <hyau@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Imre Deak <imre.deak@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Convert the board-rx51 smc91x code to be generic and make
the boards to use it. This allows future recalculation of the
timings when the source clock gets scaled.
Also correct the rx51 interrupt to be IORESOURCE_IRQ_HIGHLEVEL.
Thanks to Paul Walmsley <paul@pwsan.com> for better GPMC timing
calculations.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add generic onenand support when connected to GPMC and make the
boards to use it.
The patch has been modified to make it more generic to support all
the boards with GPMC. The patch also remove unused prototype for
omap2_onenand_rephase(void).
Note that board-apollon.c is currently using the MTD_ONENAND_GENERIC
and setting the GPMC timings in the bootloader. Setting the GPMC
timings in the bootloader will not allow supporting frequency
scaling for the onenand source clock.
Signed-off-by: Tony Lindgren <tony@atomide.com>
By default, prevent functional wakeups from inside a module from
waking up the IVA2. Let DSP Bridge code handle this when loaded.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Add D2D clocks (modem_fck, sad2d_ick, mad2d_ick) to clock framework
and ensure that auto-idle bits are set for these clocks during PRCM
init.
Also add omap3_d2d_idle() function called durint PRCM setup which
ensures D2D pins are MUX'd correctly to enable retention for
standalone (no-modem) devices.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch makes it possible to change uart sleep timeout. New sysfs
entry is added (/sys/devices/platform/serial8250.<uart>/sleep_timeout)
Writing zero will disable the timeout feature and prevent UART clocks
from being disabled.
Also default timeout is increased to 5 second to make serial console
more usable.
Original patch was written by Tero Kristo.
Cc: Tero Kristo <Tero.Kristo@nokia.com>
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch allows the UART clocks to be disabled when the OMAP UARTs
are inactive, thus permitting the chip to hit retention in idle.
After the expiration of an activity timer, each UART is allowed to
disable its clocks so the system can enter retention. The activity
timer is (re)activated on any UART interrupt, UART wake event or any
IO pad wakeup. The actual disable of the UART clocks is done in the
'prepare_idle' hook called from the OMAP idle loop.
While the activity timer is active, the smart-idle mode of the UART is
also disabled. This is due to a "feature" of the UART module that
after a UART wakeup, the smart-idle mode may be entered before the
UART has communicated the interrupt, or upon TX, an idle mode may be
entered before the TX FIFOs are emptied.
Upon suspend, the 'prepare_suspend' hook cancels any pending activity
timers and allows the clocks to be disabled immediately.
In addition, upon disabling clocks the UART state is saved in case
of an off-mode transition while clocks are off.
Special thanks to Tero Kristo for the initial ideas and first versions
of UART idle support, and to Jouni Hogander for extra testing and
bugfixes.
Tested on OMAP3 (Beagle, RX51, SDP, EVM) and OMAP2 (n810)
Cc: Tero Kristo <tero.kristo@nokia.com>
Cc: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Add common omap2/3 function to check wether there is irq pending.
Switch to use it in omap2 pm code instead of its own.
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch is to sync the core linux-omap PM code with mainline. This
code has evolved and been used for a while the linux-omap tree, but
the attempt here is to finally get this into mainline.
Following this will be a series of patches from the 'PM branch' of the
linux-omap tree to add full PM hardware support from the linux-omap
tree.
Much of this PM core code was written by Jouni Hogander with
significant contributions from Paul Walmsley as well as many others
from Nokia, Texas Instruments and linux-omap community.
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This reverts commit 5461af5af5.
Adding a disable hook to the irq_chip is not the way to fix the
problem being addressed by this patch. Instead, we need to fix
support for [enable|disable]_irq_wake().
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
We don't necessarily want to compile in irq.o and sdrc.o for omap4.
Also, clock and prcm may not be implemented initially.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Remove OMAP_PRM_REGADDR and use processor specific defines instead.
Also fold in a patch from Kevin Hilman to add _OFFSET #defines
for the PRCM registers to be used with the prm_[read|write]_* macros.
These are used extensively in the forthcoming OMAP PM support.
Also remove now unused OMAP2_PRM_BASE.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use processor specific defines instead.
As an extra bonus, this patch fixes the problem of CONFIG_DEBUG_SPINLOCK
calling sched_clock before we have things initialized:
http://patchwork.kernel.org/patch/15810/
Signed-off-by: Tony Lindgren <tony@atomide.com>
We don't necessarily want to compile in irq.o and sdrc.o for omap4.
Also, clock and prcm may not be implemented initially.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Remove OMAP_PRM_REGADDR and use processor specific defines instead.
Also fold in a patch from Kevin Hilman to add _OFFSET #defines
for the PRCM registers to be used with the prm_[read|write]_* macros.
These are used extensively in the forthcoming OMAP PM support.
Also remove now unused OMAP2_PRM_BASE.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use processor specific defines instead.
As an extra bonus, this patch fixes the problem of CONFIG_DEBUG_SPINLOCK
calling sched_clock before we have things initialized:
http://patchwork.kernel.org/patch/15810/
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently "tidspbridge" driver uses its own mmu implementation and
will migrate to use this "omap iommu" eventually. This config is
provided to make this migration happen smoothly.
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
This makes the framebuffer work on omap3.
Also fix the clk_get usage for checkpatch.pl
"ERROR: do not use assignment in if condition".
Cc: Imre Deak <imre.deak@nokia.com>
Cc: linux-fbdev-devel@lists.sourceforge.net
Acked-by: Krzysztof Helt <krzysztof.h1@wp.pl>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The OMAP3430ES2_SAVEANDRESTORE_SHIFT macro is used
by powerdomain code in
"1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT" manner, but
the definition was also (1 << 4), meaning we actually
modified bit 16. So the definition needs to be 4.
This fixes also a cold reset HW bug in OMAP3430 ES3.x
where some of the efuse bits are not isolated during
wake-up from off mode. This can cause randomish
cold resets with off mode. Enabling the USBTLL hardware
SAVEANDRESTORE causes the core power up assert to be
delayed in a way that we will not get faulty values
when boot ROM is reading the unisolated registers.
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Rename clk_init_one() to clk_preinit() to distinguish its function
from clk_init() and the individual struct clk init functions.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
On our system we see the following messages:
Disabling unused clock "gpt2_ick"
Disabling unused clock "gpt3_ick"
Disabling unused clock "gpt4_ick"
Disabling unused clock "gpt5_ick"
...
The messages have KERN_INFO level and if you have serial
console, they normally go there. I do not think it is good
idea to print that much stuff there. Moreover, messages
are not properly prefixed and for mortals it is not
immeadietly clear where they come from.
Let's give them debugging level instead.
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: trimmed debugging output in patch description]
The CORE DPLL M2 frequency change code should use pr_debug(), not
pr_info(), for its debug messages. Same with
omap2_clksel_round_rate_div(). While here, convert a few printk(KERN_ERR ..
into pr_err().
Signed-off-by: Paul Walmsley <paul@pwsan.com>
According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the
DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC
clock frequency from 83MHz to 166MHz. CDP code unconditionally
unlocked the DLL whenever shifting to a lower SDRC speed, but this
seems unnecessary and error-prone, as the DLL is no longer able to
compensate for process, voltage, and temperature variations. Instead,
only unlock the DLL when the SDRC clock rate would be less than 83MHz.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Renumber registers in omap3_sram_configure_core_dpll() assembly code to
make space for additional parameters.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Initialize SDRC_POWER to a known-good setting when the kernel boots.
Necessary since some bootloaders don't initialize SDRC_POWER properly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Clear the SDRC_POWER.PWRENA bit before putting the SDRAM into self-refresh
mode. This prevents the SDRC from attempting to power off the SDRAM,
which can cause the system to hang.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add more barriers in the SRAM CORE DPLL M2 divider change code.
- Add a DSB SY after the function's entry point to flush all cached
and buffered writes and wait for the interconnect to claim that they
have completed[1]. The idea here is to force all delayed write
traffic going to the SDRAM to at least post to the L3 interconnect
before continuing. If these writes are allowed to occur after the
SDRC is idled, the writes will not be acknowledged and the ARM will
stall.
Note that in this case, it does not matter if the writes actually
complete to the SDRAM - it is only necessary for the writes to leave
the ARM itself. If the writes are posted by the interconnect when
the SDRC goes into idle, the writes will be delayed until the SDRC
returns from idle[2]. If the SDRC is in the middle of a write when
it is requested to enter idle, the SDRC will not acknowledge the
idle request until the writes complete to the SDRAM.[3]
The old-style DMB in sdram_in_selfrefresh is now superfluous, so,
remove it.
- Add an ISB before the function's exit point to prevent the ARM from
speculatively executing into SDRAM before the SDRAM is enabled[4].
...
1. ARMv7 ARM (DDI 0406A) A3-47, A3-48.
2. Private communication with Richard Woodruff <r-woodruff2@ti.com>.
3. Private communication with Richard Woodruff <r-woodruff2@ti.com>.
4. ARMv7 ARM (DDI 0406A) A3-48.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
With the clkdev, musb_core.c needs to register clock with name "ick".
Once all the platforms using the musb driver have been converted
to use clockdev, the clock name does not need to be passed
from the low-level init code.
Signed-off-by: Tony Lindgren <tony@atomide.com>
SPI driver will do unhandled fault on OMAP2420 if trying to probe
non-existing SPI busses. Register those additional busses runtime only
for cpus having them.
Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Fix "tusb6010 init error 5, -19" and compilation warning from function
tusb6010_platform_retime "warning: 'sysclk_ps' is used uninitialized in this
function".
I suppose commit c094ba34b8f780885d029ce3c2715a194b780e5d was meant to test
for zero fclk_ps instead of sysclk_ps.
Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com>
Cc: Roel Kluin <roel.kluin@gmail.com>
Tested-by: Kalle Valo <kalle.valo@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPIO de-bounce clocks don't have any impact on the module idle state, so
the clock code should not wait for the module to enable after the de-bounce
clocks are enabled.
Problem found by Kevin Hilman <khilman@deeprootsystems.com>.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The structure 'arch_mmu' accommodates the difference between omap1 and
omap2/3.
This patch provides omap2/3 specific functions
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Add a function omap2_gp_clockevent_set_gptimer() for board-*.c files
to use in .init_irq functions to configure the system tick GPTIMER.
Practical choices at this point are GPTIMER1 or GPTIMER12. Both of
these timers are in the WKUP powerdomain, and so are unaffected by
chip power management. GPTIMER1 can use sys_clk as a source, for
applications where a high-resolution timer is more important than
power management. GPTIMER12 has the special property that it has the
secure 32kHz oscillator as its source clock, which may be less prone
to glitches than the off-chip 32kHz oscillator. But on HS devices, it
may not be available for Linux use.
It appears that most boards are fine with GPTIMER1, but BeagleBoard
should use GPTIMER12 when using a 32KiHz timer source, due to hardware bugs
in revisions B4 and below. Modify board-omap3beagle.c to use GPTIMER12.
This patch originally used a Kbuild config option to select the GPTIMER,
but was changed to allow this to be specified in board-*.c files, per
Tony's request.
Kalle Vallo <kalle.valo@nokia.com> found a bug in an earlier version of
this patch - thanks Kalle.
Tested on Beagle rev B4 ES2.1, with and without CONFIG_OMAP_32K_TIMER, and
3430SDP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Cc: Kalle Valo <kalle.valo@nokia.com>
This patch avoids waiting for the camera module to become ready,
since it doesn't have IDLEST bit.
Based on a earlier hack done by Paul Walmsley on Sep 9 2008 on
linux-omap tree.
Signed-off-by: Sergio Aguirre <saaguirre@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Commit 8ad8ff6548 breaks the OMAP2xxx
cpu_mask code, which causes OMAP2xxx to panic on boot. Fix by
removing the cpu_mask auto variable and by changing CK_242X
and CK_243X to use RATE_IN_242X/RATE_IN_243X.
Resolves
<1>Unable to handle kernel NULL pointer dereference at virtual address 0000000c
<1>pgd = c0004000
<1>[0000000c] *pgd=00000000
Internal error: Oops: 5 [#1]
Modules linked in:
CPU: 0 Not tainted (2.6.29-omap1 #32)
PC is at omap2_clk_set_parent+0x104/0x120
LR is at omap2_clk_set_parent+0x28/0x120
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Jarkko Nikula <jarkko.nikula@nokia.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
SPURIOUSIRQ is contained in bits 31:7 of INTC_SIR, so
INTC_SIR must be right shifted by 7, not 6.
No change in logic, only changes for better readability.
Refer to register definition of INTCPS_SIR_IRQ in OMAP3 Manual.
Signed-off-by: Roger Quadros <ext-roger.quadros@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
In linus' git tree the functions can be found at:
vi arch/arm/mach-omap2/usb-tusb6010.c +200 - tusb6010_platform_retime()
vi arch/arm/mach-omap2/gpmc.c +94 - gpmc_get_fclk_period()
vi arch/arm/mach-omap2/usb-tusb6010.c +53 - tusb_set_async_mode()
vi arch/arm/mach-omap2/usb-tusb6010.c +111 - tusb_set_sync_mode()
is -ENODEV appropriate when sysclk_ps == 0?
This was found by code analysis, please review.
------------------------------>8-------------8<---------------------------------
gpmc_get_fclk_period() may return 0 when gpmc_l3_clk is not enabled. This is
not checked in tusb6010_platform_retime() nor in tusb_set_async_mode() it
seems. In tusb_set_sync_mode() this may result in a division by zero.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
There is no anymore legacy driver for OMAP24XX Enhanced Audio Controller
in linux-omap and it was newer in mainline so cleanup these unneeded
defines and initialization code.
Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This should be done with GPIO calls. Patches against the
mainline tree welcome to add the necessary working functionality
back.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit 3f0a820c4c breaks OMAP2xxx boot
during initial propagate_rate() on osc_ck and sys_ck. Fix by
pre-initializing all struct clks before running any other clock init
code. Incorporates review comments from Russell King
<rmk+kernel@arm.linux.org.uk>.
Resolves
<1>Unable to handle kernel NULL pointer dereference at virtual address 00000000
<1>pgd = c0004000
<1>[00000000] *pgd=00000000
Internal error: Oops: 5 [#1]
Modules linked in:
CPU: 0 Not tainted (2.6.29-omap1 #37)
PC is at propagate_rate+0x10/0x60
LR is at omap2_clk_init+0x30/0x218
...
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Jarkko Nikula <jarkko.nikula@nokia.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Pass clocksource pointer to the read() callback for clocksources. This
allows us to share the callback between multiple instances.
[hugh@veritas.com: fix powerpc build of clocksource pass clocksource mods]
[akpm@linux-foundation.org: cleanup]
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Acked-by: John Stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This is the second go through of the old DMA_nBIT_MASK macro,and there're not
so many of them left,so I put them into one patch.I hope this is the last round.
After this the definition of the old DMA_nBIT_MASK macro could be removed.
Signed-off-by: Yang Hongyang <yanghy@cn.fujitsu.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: James Bottomley <James.Bottomley@HansenPartnership.com>
Cc: Greg KH <greg@kroah.com>
Cc: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Gumstix will soon be shipping a variant of their Summit board that
includes an SMSC LAN9221 ethernet interface. This patch provides
support via the smsc911x driver when enabled in kernel config.
The Overo defconfig is not updated since the LAN9221 is an option
not present on all systems.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Acked-by: Steve Glendinning <steve.glendinning@smsc.com>
from 2.6.29, smc911x isn't maintained anymore. A new driver, smsc911x,
will replace it. so convert omap_ldp to use smsc911x driver.
Signed-off-by: Stanley.Miao <stanley.miao@windriver.com>
Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com>
This fixes a compile error caused by a mismerge while rebasing the patch:
linux-2.6/arch/arm/mach-omap2/board-rx51-peripherals.c:354:
undefined reference to `twl4030_mmc_init'
Looks like I need to also update my build scripts, just grepping for error:
in the logs is not obviously enough..
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Adds board files and related headers for Nokia RX-51
Internet Tablet.
This patch has been updated with some clean-up patches
posted earlier to linux-omap list.
Signed-off-by: Lauri Leukkunen <lauri.leukkunen@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for 3430 SDP.
Various updates have been merged into this patch from
the linux-omap list.
Patch updated to initialize regulators by David Brownell
<dbrownell@users.sourceforge.net>.
Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
An upcoming Overo expansion board includes an ADS7846 touchscreen controller.
This patch adds support via the ads7846 driver when enabled in the
kernel config.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Create a generic board-file for initializing usb
on omap2430 and omap3 boards.
Patch modified by Tony to build the module based on
CONFIG_USB_MUSB_SOC. Also merged in a patch adding
the nop xceiv from Ajay Kumar Gupta <ajay.gupta@ti.com>.
Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Acked-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Allow a cover switch to be used to cause a rescan of the
MMC slot.
Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Acked-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Resolve longstanding issue noted by Adrian Hunter: confusion
between settting VSEL=0 (which is 1.8V on MMC1) and poweroff.
Also, leave VSEL alone if we're just powering the regulator off.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Device connected to MMC3 is assumed to be self-powered, so
set_power() function is empty. It can't be omited because
host driver requires it.
Array size for hsmmc[] is specified to allocate to allocate
an instance for the third MMC controller.
Also fix a leak which happens if invalid controller id
is passed.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
When setting up HSMMC devices, pass the device nodes back so
board code can linking them to their power supply regulators.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Correct twl4030 MMC power switching: fix voltage ranges reported
for each slot, and handle them fully.
Lies corrected:
- MMC-1 doesn't support the 2.6-2.7 Volt range
- MMC-2 can't normally support anything except 1.8V
Omissions corrected
- MMC-1 *does* handle the 2.8-2.9 Volt range
- MMC-2 can handle 2.5-3.2 Volt cards, given a transceiver
Add transciever support for MMC-2; enable it for Overo and Pandora.
(Depends on something else to have set up pinmuxing for control
signals instead of as MMC2_DAT4..7 pins.)
Also shrink twl4030_hsmmc_info a smidgeon ... padding is all gone.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add 1 to buffer length for null terminator and use snprintf.
Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Acked-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds several new GPIO pins and updates
the pin naming comments.
The patch is based on earlier patches on linux-omap
list by Manikandan Pillai <mani.pillai@ti.com>,
Vaibhav Hiremath <hvaibhav@ti.com> and
David Brownell <dbrownell@users.sourceforge.net>.
Signed-off-by: Tony Lindgren <tony@atomide.com>
There is no CONFIG_I2C2_OMAP_BEAGLE in mainline and it is under
removal in linux-omap also so remove this dead code now.
Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OMAP_TAGS should vanish soon since they're not generic arm tags.
Most of them can be converted to a platform_data or parsed
from a command line like e.g. serial tag.
For OMAP_TAG_USB we just let boards call omap_usb_init()
passing a pointer to omap_usb_config.
Patch updated by Tony for mainline, basically make
n770 and h4 compile. Also folded in a fix for OSK
by David Brownell <dbrownell@users.sourceforge.net>.
Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Move the defines to the associated board file and remove
the now unnecessary header file. Also rename
OMAP34XX_ETHR_START to LDP_ETHR_START.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Move the defines to the associated board file and remove
the now unnecessary header file. Also rename
OMAP24XX_ETHR_GPIO_IRQ to H4_ETHR_GPIO_IRQ.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Move the defines to the associated board file and remove
the now unnecessary header file. Also rename
SDP2430_ETHR_GPIO_IRQ to SDP2430_ETHR_GPIO_IRQ.
Signed-off-by: Tony Lindgren <tony@atomide.com>
* master.kernel.org:/home/rmk/linux-2.6-arm: (23 commits)
[ARM] Fix virtual to physical translation macro corner cases
[ARM] update mach-types
[ARM] 5421/1: ftrace: fix crash due to tracing of __naked functions
MX1 fix include
[ARM] 5419/1: ep93xx: fix build warnings about struct i2c_board_info
[ARM] 5418/1: restore lr before leaving mcount
ARM: OMAP: board-omap3beagle: set i2c-3 to 100kHz
ARM: OMAP: Allow I2C bus driver to be compiled as a module
ARM: OMAP: sched_clock() corrected
ARM: OMAP: Fix compile error if pm.h is included
[ARM] orion5x: pass dram mbus data to xor driver
[ARM] S3C64XX: Fix s3c64xx_setrate_clksrc
[ARM] S3C64XX: sparse warnings in arch/arm/plat-s3c64xx/irq.c
[ARM] S3C64XX: sparse warnings in arch/arm/plat-s3c64xx/s3c6400-clock.c
[ARM] S3C64XX: Fix USB host clock mux list
[ARM] S3C64XX: Fix name of USB host clock.
[ARM] S3C64XX: Rename IRQ_UHOST to IRQ_USBH
[ARM] S3C64XX: Do gpiolib configuration earlier
[ARM] S3C64XX: Staticise s3c64xx_init_irq_eint()
[ARM] SMDK6410: Declare iodesc table static
...
Changing it do 100kHz is needed to make more devices works properly. Controlling the
TI DLP Pico projector[1] doesn't work properly at 400kHz, 100kHz and lower work fine.
EDID readout is unaffected by this change.
[1] http://focus.ti.com/dlpdmd/docs/dlpdiscovery.tsp?sectionId=60&tabId=2234
Signed-off-by: Koen Kooi <koen@beagleboard.org>
Acked-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Richard Woodruff writes:
| The historic usage of this has been against single use leaf clocks
| (1st instance of gptimer). When it was used it did:
| clk_get()
| clk_set_parent()
| clk_enable()
|
| This usage was ok for that. Use on a disabled clock is needed.
|
| If there are multiple users on the clock or it is enabled there are
| problems.
|
| The call can still be unfriendly if 2 different drivers are using the
| clock with their own clock get/enable. It might be the function should
| return an error if usecount != 0 to stop surprises. It is all around
| better if the parenting is done when the clock is off.
This is a good reason to ensure that the clock is not enabled when
clk_set_parent() is called.
Acked-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The following patch enables SMC911x support to work on the OMAP LDP
board. Although the SMC911x driver will eventually be obsoleted, the
smsc911x patches are rather invasive for the -rc kernels.
Rather than risk destablising smsc911x, this simpler patch is preferred
to allow the network interface to work.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Use pr_err() for errors rather than pr_debug(). pr_debug() are
compiled away unless -DDEBUG is used.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Richard Woodruff writes that chip errata prevent USBTLL SAR from working
on OMAP3 ES levels before ES3.1:
http://marc.info/?l=linux-arm-kernel&m=123319614808833&w=2
Update the OMAP3 powerdomain structures appropriately.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Some OMAP3 chip behaviors change in ES levels after ES2. Modify the
existing omap_chip flags to add options for ES3.0 and ES3.1.
Add a new macro, CHIP_GE_OMAP3430ES2, to cover ES levels from ES2
onwards - a common pattern for OMAP3 features. Update all current
users of the omap_chip macros to use this new macro.
Also add CHIP_GE_OMAP3430ES3_1 to cover the USBTLL SAR errata case
(described and fixed in the following patch)
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When changing the parent of a clock, it is necessary to keep the
clock use counts balanced otherwise things the parent state will
get corrupted. Since we already disable and re-enable the clock,
we might as well use the recursive versions instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
_omap2_clksel_get_src_field() was returning the first entry which was
either the default _or_ applicable to the SoC. This is wrong - we
should be returning the first default which is applicable to the SoC.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The error checks for omap2_divisor_to_clksel() and comment disagree with
the actual value returned on error. Fix this to return the correct error
value.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
linux-omap source commit 33d000c99ee393fe2042f93e8422f94976d276ce
introduces a way to "dry run" clock changes before they're committed.
However, this involves putting logic to handle this into each and
every recalc function, and unfortunately due to the caching, led to
some bugs.
Solve both of issues by making the recalc methods always return the
clock rate for the clock, which the caller decides what to do with.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Clock rate change code executes inside a spinlock with hardirqs
disabled. The only code that should be messing around with the
hardirq state should be the plat-omap/clock.c code. In the
omap2_reprogram_dpllcore() case, this probably just wastes cycles, but
in the omap3_core_dpll_m2_set_rate() case, this is a nasty bug.
linux-omap source commit is b9b6208dadb5e0d8b290900a3ffa911673ca97ed.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Based on a patch from Paul Walmsley <paul@pwsan.com>:
omap2_clk_enable() should enable a clock's clockdomain before
attempting to enable its parent clock's clockdomain. Similarly, in
the unlikely event that the parent clock enable fails, the clockdomain
should be disabled.
linux-omap source commit is 6d6e285e5a7912b1ea68fadac387304c914aaba8.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Based upon a patch from Paul Walmsley <paul@pwsan.com>:
If _omap2_clk_enable() fails, the clock's usecount must be decremented
by one no matter whether the clock has a parent or not.
but reorganised a bit.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Several parts of the OMAP2/3 clock code use wmb() to try to ensure
that the hardware write completes before continuing. This approach is
problematic: wmb() only ensures that the write leaves the ARM. It
does not ensure that the write actually reaches the endpoint device.
The endpoint device in this case - either the PRM, CM, or SCM - is
three interconnects away from the ARM - and the final interconnect is
low-speed. And the OCP interconnects will post the write, and who
knows how long that will take to complete. So the wmb() is not what
we want. Worse, the wmb() is indiscriminate; it causes the ARM to
flush any other unrelated buffered writes and wait for the local
interconnect to acknowledge them - potentially very expensive.
Fix this by converting the wmb()s into readbacks of the same PRM/CM/SCM
register. Since the PRM/CM/SCM devices use a single OCP thread, this
will cause the MPU to block while waiting for posted writes to that device
to complete.
linux-omap source commit is 260f5487848681b4d8ea7430a709a601bbcb21d1.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Consolidate the commit code for DELAYED_APP clocks into a subroutine,
_omap2xxx_clk_commit(). Also convert the MPU barrier wmb() into an
OCP barrier, since with an MPU barrier, we have no guarantee that the
write actually reached the endpoint device.
linux-omap source commit is 0f5bdb736515801b296125d16937a21ff7b3cfdc.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
clk_disable() previously used an ARM barrier, wmb(), to try to ensure
that the hardware write completed before continuing. There are some
problems with this approach.
The first problem is that wmb() only ensures that the write leaves the
ARM -- not that it actually reaches the endpoint device. In this
case, the endpoint device - either the PRM, CM, or SCM - is three
interconnects away from the ARM, and the final interconnect is
low-speed. And the OCP interconnects will post the write, who knows
how long that will take to complete. So the wmb() is not really what
we want.
Worse, the wmb() is indiscriminate; it will cause the ARM to flush any
other unrelated buffered writes and wait for the local interconnect to
acknowledge them - potentially very expensive.
This first problem could be fixed by doing a readback of the same PRM/CM/SCM
register. Since these devices use a single OCP thread, this will cause the
MPU to wait for the write to complete.
But the primary problem is a conceptual one: clk_disable() should not
need any kind of barrier. clk_enable() needs one since device driver
code must not access a device until its clocks are known to be
enabled. But clk_disable() has no such restriction.
Since blocking the MPU on a PRM/CM/SCM write can be a very
high-latency operation - several hundred MPU cycles - it's worth
avoiding this barrier if possible.
linux-omap source commit is f4aacad2c0ed1055622d5c1e910befece24ef0e2.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Traditionally, we've tracked the parent/child relationships between
clk structures by setting the child's parent member to point at the
upstream clock. As a result, when decending the tree, we have had
to scan all clocks to find the children.
Avoid this wasteful scanning by keeping a list of the clock's children.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This implements the remainder of:
OMAP clock: move rate recalc, propagation code up to plat-omap/clock.c
from Paul Walmsley which is not covered by the previous:
[ARM] omap: move clock propagation into core omap clock code
[ARM] omap: remove unnecessary calls to propagate_rate()
[ARM] omap: move propagate_rate() calls into generic omap clock code
commits.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Use the standard clk_set_rate() function in omap2_clk_arch_init()
rather than omap2_select_table_rate() -- this will ensure that clock
rates are recalculated and propagated correctly after those operations
are consolidated into clk_set_rate().
linux-omap source commit is 03c03330017eeb445b01957608ff5db49a7151b6.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Current implementation will disable clocks in the order defined in clock34xx.h,
at least DPLL4_M2X2 will hang in certain cases (and prevent retention / off)
if clocks are not disabled in correct order. This patch makes sure the parent
clocks will be active when disabling a clock.
linux-omap source commit is 672680063420ef8c8c4e7271984bb9cc08171d29.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add the omap3_core_dpll_m2_set_rate() function to the OMAP3 clock code,
which calls into the SRAM function omap3_sram_configure_core_dpll() to
change the CORE DPLL M2 divider. (SRAM code is necessary since rate changes
on clocks upstream from the SDRC can glitch SDRAM accesses.)
Use this function for the set_rate function pointer in the dpll3_m2_ck
struct clk. With this function in place, PM/OPP code should be able to
alter SDRAM speed via code similar to:
clk_set_rate(&dpll3_m2_ck, target_rate).
linux-omap source commit is 7f8b2b0f4fe52238c67d79dedcd2794dcef4dddd.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
For a given SDRAM clock rate, SDRAM chips require memory controllers
to use a specific set of timing minimums and maximums to transfer data
reliably. These parameters can be different for different memory chips
and can also potentially vary by board.
This patch adds the infrastructure for board-*.c files to pass this
timing data to the SDRAM controller init function. The timing data is
specified in an 'omap_sdrc_params' structure, in terms of SDRC
controller register values. An array of these structs, one per SDRC
target clock rate, is passed by the board-*.c file to
omap2_init_common_hw().
This patch does not define the values for different memory chips, nor
does it use the values for anything; those will come in subsequent patches.
linux-omap source commit is bc84ecfc795c2d1c5cda8da4127cf972f488a696.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Separate SDRC code common to OMAP2/3 from mach-omap2/sdrc2xxx.c to
mach-omap2/sdrc.c. Rename the OMAP2xxx-specific functions to use an
'omap2xxx' prefix rather than an 'omap2' prefix, and use "sdrc" in the
function names rather than "memory." Mark several functions
as static that should not be used outside the sdrc2xxx.c file.
linux-omap source commit is bf1612b9d8d29379558500cd5de9ae0367c41fc4.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rename arch/arm/mach-omap2/memory.c to arch/arm/mach-omap2/sdrc2xxx.c, since
it contains exclusively SDRAM-related functions. Most of the functions
are also OMAP2xxx-specific - those which are common will be separated out
in a following patch.
linux-omap source commit is fe212f797e2efef9dc88bcb5db7cf9db3f9f562e.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Move the contents of the arch/arm/mach-omap2/memory.h file to the
existing mach/sdrc.h file, and remove memory.h. Modify files which
include memory.h to include asm/arch/sdrc.h instead.
linux-omap source commit is e7ae2d89921372fc4b9712a32cc401d645597807.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
