Merge branch 'omap-clock-upstream' of git://git.pwsan.com/linux-2.6 into for-next
This commit is contained in:
Tony Lindgren
commit
88b6f7eb9b
10 changed files with 128 additions and 86 deletions
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@ -776,7 +776,7 @@ int __init omap1_clk_init(void)
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arm_idlect1_mask = ~0;
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for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
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clk_init_one(c->lk.clk);
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clk_preinit(c->lk.clk);
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cpu_mask = 0;
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if (cpu_is_omap16xx())
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@ -547,8 +547,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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const struct clksel_rate *clkr;
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u32 last_div = 0;
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printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
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clk->name, target_rate);
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pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
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clk->name, target_rate);
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*new_div = 1;
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@ -562,7 +562,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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/* Sanity check */
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if (clkr->div <= last_div)
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printk(KERN_ERR "clock: clksel_rate table not sorted "
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pr_err("clock: clksel_rate table not sorted "
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"for clock %s", clk->name);
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last_div = clkr->div;
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@ -574,7 +574,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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}
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if (!clkr->div) {
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printk(KERN_ERR "clock: Could not find divisor for target "
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pr_err("clock: Could not find divisor for target "
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"rate %ld for clock %s parent %s\n", target_rate,
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clk->name, clk->parent->name);
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return ~0;
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@ -582,8 +582,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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*new_div = clkr->div;
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printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
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(clk->parent->rate / clkr->div));
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pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
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(clk->parent->rate / clkr->div));
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return (clk->parent->rate / clkr->div);
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}
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@ -1035,7 +1035,7 @@ void omap2_clk_disable_unused(struct clk *clk)
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if ((regval32 & (1 << clk->enable_bit)) == v)
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return;
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printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
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printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name);
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if (cpu_is_omap34xx()) {
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omap2_clk_enable(clk);
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omap2_clk_disable(clk);
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@ -725,7 +725,7 @@ int __init omap2_clk_init(void)
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clk_init(&omap2_clk_functions);
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for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
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clk_init_one(c->lk.clk);
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clk_preinit(c->lk.clk);
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osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
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propagate_rate(&osc_ck);
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@ -281,6 +281,8 @@ static struct omap_clk omap34xx_clks[] = {
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#define MAX_DPLL_WAIT_TRIES 1000000
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#define MIN_SDRC_DLL_LOCK_FREQ 83000000
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/**
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* omap3_dpll_recalc - recalculate DPLL rate
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* @clk: DPLL struct clk
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@ -703,6 +705,7 @@ static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
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static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 new_div = 0;
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u32 unlock_dll = 0;
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unsigned long validrate, sdrcrate;
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struct omap_sdrc_params *sp;
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@ -729,17 +732,22 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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if (!sp)
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return -EINVAL;
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pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
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validrate);
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pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
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sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
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if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
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pr_debug("clock: will unlock SDRC DLL\n");
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unlock_dll = 1;
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}
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pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
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validrate);
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pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
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sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
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/* REVISIT: SRAM code doesn't support other M2 divisors yet */
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WARN_ON(new_div != 1 && new_div != 2);
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/* REVISIT: Add SDRC_MR changing to this code also */
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omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
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sp->actim_ctrlb, new_div);
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sp->actim_ctrlb, new_div, unlock_dll);
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return 0;
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}
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@ -956,7 +964,7 @@ int __init omap2_clk_init(void)
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clk_init(&omap2_clk_functions);
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for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
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clk_init_one(c->lk.clk);
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clk_preinit(c->lk.clk);
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for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
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if (c->cpu & cpu_clkflg) {
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@ -37,6 +37,10 @@ static struct omap_sdrc_params *sdrc_init_params;
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void __iomem *omap2_sdrc_base;
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void __iomem *omap2_sms_base;
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/* SDRC_POWER register bits */
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#define SDRC_POWER_EXTCLKDIS_SHIFT 3
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#define SDRC_POWER_PWDENA_SHIFT 2
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#define SDRC_POWER_PAGEPOLICY_SHIFT 0
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/**
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* omap2_sdrc_get_params - return SDRC register values for a given clock rate
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@ -74,7 +78,14 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
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omap2_sms_base = omap2_globals->sms;
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}
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/* turn on smart idle modes for SDRAM scheduler and controller */
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/**
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* omap2_sdrc_init - initialize SMS, SDRC devices on boot
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* @sp: pointer to a null-terminated list of struct omap_sdrc_params
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*
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* Turn on smart idle modes for SDRAM scheduler and controller.
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* Program a known-good configuration for the SDRC to deal with buggy
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* bootloaders.
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*/
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void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
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{
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u32 l;
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@ -90,4 +101,10 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
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sdrc_write_reg(l, SDRC_SYSCONFIG);
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sdrc_init_params = sp;
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/* XXX Enable SRFRONIDLEREQ here also? */
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l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
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(1 << SDRC_POWER_PWDENA_SHIFT) |
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(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
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sdrc_write_reg(l, SDRC_POWER);
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}
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@ -40,69 +40,74 @@
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/*
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* Change frequency of core dpll
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* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
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* r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
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* SDRC rates < 83MHz
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*/
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ENTRY(omap3_sram_configure_core_dpll)
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stmfd sp!, {r1-r12, lr} @ store regs to stack
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ldr r4, [sp, #52] @ pull extra args off the stack
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dsb @ flush buffered writes to interconnect
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cmp r3, #0x2
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blne configure_sdrc
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cmp r3, #0x2
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cmp r4, #0x1
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bleq unlock_dll
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blne lock_dll
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cmp r3, #0x1
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blne unlock_dll
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bl sdram_in_selfrefresh @ put the SDRAM in self refresh
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bl configure_core_dpll
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bl enable_sdrc
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cmp r3, #0x1
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blne wait_dll_unlock
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cmp r3, #0x2
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cmp r4, #0x1
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bleq wait_dll_unlock
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blne wait_dll_lock
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cmp r3, #0x1
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blne configure_sdrc
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isb @ prevent speculative exec past here
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mov r0, #0 @ return value
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ldmfd sp!, {r1-r12, pc} @ restore regs and return
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unlock_dll:
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ldr r4, omap3_sdrc_dlla_ctrl
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ldr r5, [r4]
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orr r5, r5, #0x4
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str r5, [r4]
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ldr r11, omap3_sdrc_dlla_ctrl
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ldr r12, [r11]
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orr r12, r12, #0x4
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str r12, [r11] @ (no OCP barrier needed)
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bx lr
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lock_dll:
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ldr r4, omap3_sdrc_dlla_ctrl
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ldr r5, [r4]
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bic r5, r5, #0x4
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str r5, [r4]
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ldr r11, omap3_sdrc_dlla_ctrl
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ldr r12, [r11]
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bic r12, r12, #0x4
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str r12, [r11] @ (no OCP barrier needed)
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bx lr
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sdram_in_selfrefresh:
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mov r5, #0x0 @ Move 0 to R5
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mcr p15, 0, r5, c7, c10, 5 @ memory barrier
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ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
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ldr r5, [r4] @ read the contents of SDRC_POWER
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orr r5, r5, #0x40 @ enable self refresh on idle req
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str r5, [r4] @ write back to SDRC_POWER register
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ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
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ldr r5, [r4]
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bic r5, r5, #0x2 @ disable iclk bit for SRDC
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str r5, [r4]
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ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
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ldr r12, [r11] @ read the contents of SDRC_POWER
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mov r9, r12 @ keep a copy of SDRC_POWER bits
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orr r12, r12, #0x40 @ enable self refresh on idle req
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bic r12, r12, #0x4 @ clear PWDENA
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str r12, [r11] @ write back to SDRC_POWER register
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ldr r12, [r11] @ posted-write barrier for SDRC
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ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
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ldr r12, [r11]
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bic r12, r12, #0x2 @ disable iclk bit for SDRC
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str r12, [r11]
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wait_sdrc_idle:
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ldr r4, omap3_cm_idlest1_core
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ldr r5, [r4]
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and r5, r5, #0x2 @ check for SDRC idle
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cmp r5, #2
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ldr r11, omap3_cm_idlest1_core
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ldr r12, [r11]
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and r12, r12, #0x2 @ check for SDRC idle
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cmp r12, #2
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bne wait_sdrc_idle
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bx lr
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configure_core_dpll:
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ldr r4, omap3_cm_clksel1_pll
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ldr r5, [r4]
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ldr r6, core_m2_mask_val @ modify m2 for core dpll
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and r5, r5, r6
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orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val
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str r5, [r4]
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mov r5, #0x800 @ wait for the clock to stabilise
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ldr r11, omap3_cm_clksel1_pll
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ldr r12, [r11]
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ldr r10, core_m2_mask_val @ modify m2 for core dpll
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and r12, r12, r10
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orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
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str r12, [r11]
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ldr r12, [r11] @ posted-write barrier for CM
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mov r12, #0x800 @ wait for the clock to stabilise
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cmp r3, #2
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bne wait_clk_stable
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bx lr
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wait_clk_stable:
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subs r5, r5, #1
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subs r12, r12, #1
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bne wait_clk_stable
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nop
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nop
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@ -116,42 +121,42 @@ wait_clk_stable:
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nop
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bx lr
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enable_sdrc:
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ldr r4, omap3_cm_iclken1_core
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ldr r5, [r4]
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orr r5, r5, #0x2 @ enable iclk bit for SDRC
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str r5, [r4]
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ldr r11, omap3_cm_iclken1_core
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ldr r12, [r11]
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orr r12, r12, #0x2 @ enable iclk bit for SDRC
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str r12, [r11]
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wait_sdrc_idle1:
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ldr r4, omap3_cm_idlest1_core
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ldr r5, [r4]
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and r5, r5, #0x2
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cmp r5, #0
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ldr r11, omap3_cm_idlest1_core
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ldr r12, [r11]
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and r12, r12, #0x2
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cmp r12, #0
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bne wait_sdrc_idle1
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ldr r4, omap3_sdrc_power
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ldr r5, [r4]
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bic r5, r5, #0x40
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str r5, [r4]
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restore_sdrc_power_val:
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ldr r11, omap3_sdrc_power
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str r9, [r11] @ restore SDRC_POWER, no barrier needed
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bx lr
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wait_dll_lock:
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ldr r4, omap3_sdrc_dlla_status
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ldr r5, [r4]
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and r5, r5, #0x4
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cmp r5, #0x4
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ldr r11, omap3_sdrc_dlla_status
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ldr r12, [r11]
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and r12, r12, #0x4
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cmp r12, #0x4
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bne wait_dll_lock
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bx lr
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wait_dll_unlock:
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ldr r4, omap3_sdrc_dlla_status
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ldr r5, [r4]
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and r5, r5, #0x4
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cmp r5, #0x0
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ldr r11, omap3_sdrc_dlla_status
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ldr r12, [r11]
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and r12, r12, #0x4
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cmp r12, #0x0
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bne wait_dll_unlock
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bx lr
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configure_sdrc:
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ldr r4, omap3_sdrc_rfr_ctrl
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str r0, [r4]
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ldr r4, omap3_sdrc_actim_ctrla
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str r1, [r4]
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ldr r4, omap3_sdrc_actim_ctrlb
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str r2, [r4]
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ldr r11, omap3_sdrc_rfr_ctrl
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str r0, [r11]
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ldr r11, omap3_sdrc_actim_ctrla
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str r1, [r11]
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ldr r11, omap3_sdrc_actim_ctrlb
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str r2, [r11]
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ldr r2, [r11] @ posted-write barrier for SDRC
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bx lr
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omap3_sdrc_power:
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@ -240,13 +240,13 @@ void recalculate_root_clocks(void)
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}
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/**
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* clk_init_one - initialize any fields in the struct clk before clk init
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* clk_preinit - initialize any fields in the struct clk before clk init
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* @clk: struct clk * to initialize
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*
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* Initialize any struct clk fields needed before normal clk initialization
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* can run. No return value.
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*/
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void clk_init_one(struct clk *clk)
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void clk_preinit(struct clk *clk)
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{
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INIT_LIST_HEAD(&clk->children);
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}
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@ -119,7 +119,7 @@ struct clk_functions {
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extern unsigned int mpurate;
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extern int clk_init(struct clk_functions *custom_clocks);
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extern void clk_init_one(struct clk *clk);
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extern void clk_preinit(struct clk *clk);
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extern int clk_register(struct clk *clk);
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extern void clk_reparent(struct clk *child, struct clk *parent);
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extern void clk_unregister(struct clk *clk);
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@ -23,7 +23,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
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extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
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u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb, u32 m2);
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u32 sdrc_actim_ctrlb, u32 m2,
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u32 unlock_dll);
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/* Do not use these */
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extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
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@ -60,7 +61,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
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extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
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u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb, u32 m2);
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u32 sdrc_actim_ctrlb, u32 m2,
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u32 unlock_dll);
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extern unsigned long omap3_sram_configure_core_dpll_sz;
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#endif
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|
|
|
|||
|
|
@ -201,6 +201,15 @@ void __init omap_map_sram(void)
|
|||
base = OMAP3_SRAM_PA;
|
||||
base = ROUND_DOWN(base, PAGE_SIZE);
|
||||
omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
|
||||
|
||||
/*
|
||||
* SRAM must be marked as non-cached on OMAP3 since the
|
||||
* CORE DPLL M2 divider change code (in SRAM) runs with the
|
||||
* SDRAM controller disabled, and if it is marked cached,
|
||||
* the ARM may attempt to write cache lines back to SDRAM
|
||||
* which will cause the system to hang.
|
||||
*/
|
||||
omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
|
||||
}
|
||||
|
||||
omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
|
||||
|
|
@ -343,14 +352,15 @@ static inline int omap243x_sram_init(void)
|
|||
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
|
||||
u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb,
|
||||
u32 m2);
|
||||
u32 m2, u32 unlock_dll);
|
||||
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb, u32 m2)
|
||||
u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll)
|
||||
{
|
||||
BUG_ON(!_omap3_sram_configure_core_dpll);
|
||||
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
|
||||
sdrc_actim_ctrla,
|
||||
sdrc_actim_ctrlb, m2);
|
||||
sdrc_actim_ctrlb, m2,
|
||||
unlock_dll);
|
||||
}
|
||||
|
||||
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
|
||||
|
|
|
|||
Loading…
Reference in a new issue