Commit graph

296 commits

Author SHA1 Message Date
Nicolas Pitre
8a052e0bc2 [ARM] 3293/1: don't invalidate the whole I-cache with xscale_coherent_user_range
Patch from Nicolas Pitre

The mini I-cache issue is valid only for kernel space since debuggers
would not fly if they used user space addresses for their stubs.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-02-01 19:26:01 +00:00
George G. Davis
7efb83002b [ARM] 3269/1: Add ARMv6 MT_NONSHARED_DEVICE mem_types[] index
Patch from George G. Davis

This Freescale Semiconductor, Inc. contributed patch adds mem_types[]
support for ARMv6 non-shared device memory region attributes. This
implementation provides support for only first level section mapped
non-shared devices. Second level non-shared device mappings are not
yet supported.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-26 15:21:28 +00:00
Russell King
20a2c88f50 [ARM] Fix ioremap.c vfree type warning
arch/arm/mm/ioremap.c:145: warning: passing argument 1 of 'vfree' makes pointer from integer without a cast

resulted from commit id 9d4ae7276a

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-20 20:52:50 +00:00
Kevin Hilman
37134cd55d [ARM] 3209/1: Configurable DMA-consistent memory region
Patch from Kevin Hilman

This patch increase available DMA-consistent memory allocated by dma_coherent_alloc(). The default remains at 2M (defined in asm/memory.h) and each platform has the ability to override in asm/arch-foo/memory.h.

Signed-off-by: Kevin Hilman <kevin@hilman.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-12 16:12:21 +00:00
Deepak Saxena
9d4ae7276a [ARM] 3070/2: Add __ioremap_pfn() API
Patch from Deepak Saxena

In working on adding 36-bit addressed supersection support to ioremap(),
I came to the conclusion that it would be far simpler to do so by just
splitting __ioremap() into a main external interface and adding an
__ioremap_pfn() function that takes a pfn + offset into the page that
__ioremap() can call. This way existing callers of __ioremap() won't have
to change their code and 36-bit systems will just call __ioremap_pfn()
and we will not have to deal with unsigned long long variables.

Note that __ioremap_pfn() should _NOT_ be called directly by drivers
but is reserved for use by arch_ioremap() implementations that map
32-bit resource regions into the real 36-bit address and then call
this new function.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-09 19:23:11 +00:00
SAN People
73a59c1c4a [ARM] 3240/2: AT91RM9200 support for 2.6 (Core)
Patch from SAN People

Following changes were made to clock.c:

1) Replaced <asm/hardware/clock.h> with <linux/clk.h>
2) Removed old unused clk_enable & clk_disable.
3) Replaced clk_use/clk_unuse with clk_enable/clk_disable.

Otherwise it's the same as the previous patch.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-09 17:05:41 +00:00
Russell King
0fec53a24a [ARM] Remove EPXA10DB machine support
EPXA10DB seems to be uncared for:
- the "PLD" code has never been merged
- no one has reported that this platform has been broken since
  at least 2.6.10
- interest seems to have dried up around March 2003.

Therefore, remove EPXA10DB support.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-08 22:37:46 +00:00
Russell King
78ff18a412 [ARM] Cleanup ARM includes
arch/arm/kernel/entry-armv.S has contained a comment suggesting
that asm/hardware.h and asm/arch/irqs.h should be moved into the
asm/arch/entry-macro.S include.  So move the includes to these
two files as required.

Add missing includes (asm/hardware.h, asm/io.h) to asm/arch/system.h
includes which use those facilities, and remove asm/io.h from
kernel/process.c.

Remove other unnecessary includes from arch/arm/kernel, arch/arm/mm
and arch/arm/mach-footbridge.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-03 17:39:34 +00:00
Russell King
df2f5e721e [ARM SMP] Disable lazy flush_dcache_page for SMP
Lazy flush_dcache_page() causes userspace instability on SMP
platforms, so disable it for now.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-30 16:02:54 +00:00
Russell King
5edf71ae12 [ARM] Do not call flush_tlb_kernel_range() with IRQs disabled.
We must not call TLB maintainence operations with interrupts disabled,
otherwise we risk a lockup in the SMP IPI code.

This means that consistent_free() can not be called from a context with
IRQs disabled.  In addition, we must not hold the lock in consistent_free
when we call flush_tlb_kernel_range().  However, we must continue to
prevent consistent_alloc() from re-using the memory region until we've
finished tearing down the mapping and dealing with the TLB.

Therefore, leave the vm_region entry in the list, but mark it inactive
before dropping the lock and starting the tear-down process.  After the
mapping has been torn down, re-acquire the lock and remove the entry
from the list.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-25 15:52:51 +00:00
Daniel Jacobowitz
a6c61e9dfd [ARM] 3168/1: Update ARM signal delivery and masking
Patch from Daniel Jacobowitz

After delivering a signal (creating its stack frame) we must check for
additional pending unblocked signals before returning to userspace.
Otherwise signals may be delayed past the next syscall or reschedule.

Once that was fixed it became obvious that the ARM signal mask manipulation
was broken.  It was a little bit broken before the recent SA_NODEFER
changes, and then very broken after them.  We must block the requested
signals before starting the handler or the same signal can be delivered
again before the handler even gets a chance to run.

Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-19 10:01:07 +00:00
Russell King
02b3083922 [ARM] Fix some corner cases in new mm initialisation
Document that the VMALLOC_END address must be aligned to 2MB since
it must align with a PGD boundary.

Allocate the vectors page early so that the flush_cache_all() later
will cause any dirty cache lines in the direct mapping will be safely
written back.

Move the flush_cache_all() to the second local_flush_cache_tlb() and
remove the now redundant first local_flush_cache_tlb().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-17 22:43:30 +00:00
Russell King
67a1901ff4 [ARM] __ioremap doesn't use 4th argument
The "align" argument in ARMs __ioremap is unused and provides a
misleading expectation that it might do something.  It doesn't.
Remove it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-17 16:48:00 +00:00
Tony Lindgren
1dbae815a7 [ARM] 3145/1: OMAP 3a/5: Add support for omap24xx
Patch from Tony Lindgren

This patch adds support for omap24xx series of processors.
The files live in arch/arm/mach-omap2, and share common
files with omap15xx and omap16xx processors in
arch/arm/plat-omap.

Omap24xx support was originally added for 2.6.9 by TI.
This code was then improved and integrated to share common
code with omap15xx and omap16xx processors by various
omap developers, such as Paul Mundt, Juha Yrjola, Imre Deak,
Tony Lindgren, Richard Woodruff, Nishant Menon, Komal Shah
et al.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-10 14:26:51 +00:00
Tony Lindgren
3179a01939 [ARM] 3141/1: OMAP 1/5: Update omap1 specific files
Patch from Tony Lindgren

This patch syncs the mainline kernel with linux-omap tree.
The highlights of the patch are:

- Omap1 serial pport and framebuffer init updates by Imre Deak

- Add support for omap310 processor and Palm Tungsten E PDA
  by Laurent Gonzales, Romain Goyet, et al. Omap310 and
  omap1510 processors are now handled as omap15xx.

- Omap1 specific changes to shared omap clock framework
  by Tony Lindgren

- Omap1 specific changes to shared omap pin mux framework
  by Tony Lindgren

- Other misc fixes, such as update memory timings for smc91x,
  omap1 specific device initialization etc.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-10 14:26:48 +00:00
Russell King
862184fe01 [ARM SMP] Add Realview MPcore SMP support
Add SMP support for the MPcore tile fitted to the Realview ARM
platform.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-07 21:05:42 +00:00
Russell King
cd03adb081 [ARM SMP] Add support for shared memory attribute
We need to set the shared memory attribute in the page tables
on SMP systems to allow the cache coherency to operate.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-07 10:10:28 +00:00
Russell King
5f8b1178e2 [ARM] Merge SMP tree 2005-11-03 21:02:39 +00:00
Nicolas Pitre
24bcc2f46c [ARM] 3092/1: remove excessive print format padding
Patch from Nicolas Pitre

Using a llx format to print addresses that might possibly be (only) 36
bits wide make sense.  However making it a zero padded 16 char wide
field is a bit excessive and useless.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-03 20:40:50 +00:00
Russell King
4a5f79e7e6 [ARM SMP] Add configuration option for ARMv6K processors
The 'K' extension adds several new instructions to the ARMv6 ISA
which are primerily useful for SMP.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-03 15:48:21 +00:00
Russell King
6bf7bd6967 [ARM] Fix mm initialisation with write buffered write allocate caches
It seems that without the extra tlb flush, we may end up faulting
during the early kernel initialisation because the TLB can't see
the updated page tables.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-02 14:11:35 +00:00
Catalin Marinas
8ad68bbf7a [ARM] Add support for ARM RealView board
Support for RealView EB.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-31 14:25:02 +00:00
Russell King
b4c2803ca8 [ARM] Make v6 copypage function static and cleanup pgprots
We know what pgprot we're going to use, so don't #define it.  Also,
since we select the nonaliasing/aliasing copypage implementation at
run time, there's no point having it globally visible.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-30 19:03:21 +00:00
Hugh Dickins
4c21e2f244 [PATCH] mm: split page table lock
Christoph Lameter demonstrated very poor scalability on the SGI 512-way, with
a many-threaded application which concurrently initializes different parts of
a large anonymous area.

This patch corrects that, by using a separate spinlock per page table page, to
guard the page table entries in that page, instead of using the mm's single
page_table_lock.  (But even then, page_table_lock is still used to guard page
table allocation, and anon_vma allocation.)

In this implementation, the spinlock is tucked inside the struct page of the
page table page: with a BUILD_BUG_ON in case it overflows - which it would in
the case of 32-bit PA-RISC with spinlock debugging enabled.

Splitting the lock is not quite for free: another cacheline access.  Ideally,
I suppose we would use split ptlock only for multi-threaded processes on
multi-cpu machines; but deciding that dynamically would have its own costs.
So for now enable it by config, at some number of cpus - since the Kconfig
language doesn't support inequalities, let preprocessor compare that with
NR_CPUS.  But I don't think it's worth being user-configurable: for good
testing of both split and unsplit configs, split now at 4 cpus, and perhaps
change that to 8 later.

There is a benefit even for singly threaded processes: kswapd can be attacking
one part of the mm while another part is busy faulting.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:42 -07:00
Hugh Dickins
69b0475456 [PATCH] mm: arm ready for split ptlock
Prepare arm for the split page_table_lock: three issues.

Signal handling's preserve and restore of iwmmxt context currently involves
reading and writing that context to and from user space, while holding
page_table_lock to secure the user page(s) against kswapd.  If we split the
lock, then the structure might span two pages, secured by to read into and
write from a kernel stack buffer, copying that out and in without locking (the
structure is 160 bytes in size, and here we're near the top of the kernel
stack).  Or would the overhead be noticeable?

arm_syscall's cmpxchg emulation use pte_offset_map_lock, instead of
pte_offset_map and mm-wide page_table_lock; and strictly, it should now also
take mmap_sem before descending to pmd, to guard against another thread
munmapping, and the page table pulled out beneath this thread.

Updated two comments in fault-armv.c.  adjust_pte is interesting, since its
modification of a pte in one part of the mm depends on the lock held when
calling update_mmu_cache for a pte in some other part of that mm.  This can't
be done with a split page_table_lock (and we've already taken the lowest lock
in the hierarchy here): so we'll have to disable split on arm, unless
CONFIG_CPU_CACHE_VIPT to ensures adjust_pte never used.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:42 -07:00
Hugh Dickins
b462705ac6 [PATCH] mm: arches skip ptlock
Convert those few architectures which are calling pud_alloc, pmd_alloc,
pte_alloc_map on a user mm, not to take the page_table_lock first, nor drop it
after.  Each of these can continue to use pte_alloc_map, no need to change
over to pte_alloc_map_lock, they're neither racy nor swappable.

In the sparc64 io_remap_pfn_range, flush_tlb_range then falls outside of the
page_table_lock: that's okay, on sparc64 it's like flush_tlb_mm, and that has
always been called from outside of page_table_lock in dup_mmap.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:40 -07:00
Hugh Dickins
872fec16d9 [PATCH] mm: init_mm without ptlock
First step in pushing down the page_table_lock.  init_mm.page_table_lock has
been used throughout the architectures (usually for ioremap): not to serialize
kernel address space allocation (that's usually vmlist_lock), but because
pud_alloc,pmd_alloc,pte_alloc_kernel expect caller holds it.

Reverse that: don't lock or unlock init_mm.page_table_lock in any of the
architectures; instead rely on pud_alloc,pmd_alloc,pte_alloc_kernel to take
and drop it when allocating a new one, to check lest a racing task already
did.  Similarly no page_table_lock in vmalloc's map_vm_area.

Some temporary ugliness in __pud_alloc and __pmd_alloc: since they also handle
user mms, which are converted only by a later patch, for now they have to lock
differently according to whether or not it's init_mm.

If sources get muddled, there's a danger that an arch source taking
init_mm.page_table_lock will be mixed with common source also taking it (or
neither take it).  So break the rules and make another change, which should
break the build for such a mismatch: remove the redundant mm arg from
pte_alloc_kernel (ppc64 scrapped its distinct ioremap_mm in 2.6.13).

Exceptions: arm26 used pte_alloc_kernel on user mm, now pte_alloc_map; ia64
used pte_alloc_map on init_mm, now pte_alloc_kernel; parisc had bad args to
pmd_alloc and pte_alloc_kernel in unused USE_HPPA_IOREMAP code; ppc64
map_io_page forgot to unlock on failure; ppc mmu_mapin_ram and ppc64 im_free
took page_table_lock for no good reason.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:40 -07:00
Nicolas Pitre
1a47ebc0d9 [ARM] 3059/1: fix XIP support
Patch from Nicolas Pitre

Fix XIP support after recent bootmem code refactoring.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-29 16:28:29 +01:00
Linus Torvalds
83928e17b9 Merge master.kernel.org:/home/rmk/linux-2.6-arm
Minor manual fixups for gfp_t clashes.
2005-10-28 09:24:22 -07:00
Al Viro
f9e3214a79 [PATCH] gfp_t: dma-mapping (arm)
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-28 08:16:47 -07:00
Deepak Saxena
0b7cd62ecd [ARM] 3017/1: Add support for 36-bit addresses to create_mapping()
Patch from Deepak Saxena

This patch adds support for 36-bit static mapped I/O. While there
are no platforms in the tree ATM that use it, it has been tested
tested on the IXP2350 NPU and I would like to get the support for
that chipset upstream one piece at a time. There are also other
Intel chipset ports in development that are waiting on this to go
upstream.

The patch replaces the print formats for physical addresses with
%016llx which will create a bit extraneous output on 32-bit systems,
but I think that is cleaner than having #ifdefs, specially since
users will only see the output in error cases.

Depends on 3016/1.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-28 15:19:12 +01:00
Deepak Saxena
9769c2468d [ARM] 3016/1: Replace map_desc.physical with map_desc.pfn
Patch from Deepak Saxena

Convert map_desc.physical to map_desc.pfn. This allows us to add
support for 36-bit addressed physical devices in the static maps
without having to resort to u64 variables.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-28 15:19:11 +01:00
Russell King
90072059d2 [ARM] Re-jig bootmem initialisation
Make ARM independent of the way bootmem operates internally.  We
now map each node as we initialise it, and place the bootmem bitmap
inside each node, rather than all in the first node.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-28 14:48:37 +01:00
Russell King
f339ab3d6c [ARM] Fix sparse warnings
Fix sparse warnings in arch/arm/kernel/module.c,
arch/arm/mm/consistent.c, drivers/pcmcia/sa1111_generic.c,
and platform support files.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-28 14:29:43 +01:00
Russell King
674c045382 [ARM] 3/4: Remove asm/hardware.h from SA1100 io.h
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-28 14:25:28 +01:00
Tony Lindgren
67c5587ad4 [ARM] 3024/1: Add cpu_v6_proc_fin
Patch from Tony Lindgren

Machine restart calls cpu_proc_fin() to clean and disable
cache, and turn off interrupts. This patch adds proper
cpu_v6_proc_fin.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-19 23:00:56 +01:00
George G. Davis
737d0bb770 [ARM] 2969/1: miscellaneous whitespace cleanup
Patch from George G. Davis

Fix leading, trailing and other miscellaneous whitespace issues
in arch/arm/kernel/alignment.c.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-12 19:58:10 +01:00
George G. Davis
19da83f632 [ARM] 2959/1: Add test for invalid LDRD/STRD Rd cases in ARM alignment handler
Patch from George G. Davis

Add test for invalid LDRD/STRD Rd cases in ARM alignment handler
and restore SWP printk KERN_ERR.

Signed-off-by: Steve Longerbeam <slongerbeam@mvista.com>
Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-10 10:17:44 +01:00
Catalin Marinas
e03eb5272b [ARM] 2954/1: Allow D and I cache and branch prediction disabling for ARMv6
Patch from Catalin Marinas

There is no reason to not allow these config options. They are useful when
the hardware has problems.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-05 23:06:36 +01:00
Catalin Marinas
2c3a054099 [ARM] 2943/1: Clear the exclusive monitor in v6_early_abort
Patch from Catalin Marinas

Data abort caused by ldrex/strex can leave the exclusive monitor in an
unpredictable state. It is recommended that a clrex/strex is performed to
clear this state.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-02 22:34:35 +01:00
Gen FUKATSU
217874feed [ARM] 2940/1: Fix BTB entry flush in arch/arm/mm/cache-v6.S
Patch from Gen FUKATSU

Invalidate BTB entry instruction flushes two instruction
at a time. Therefore this instruction should be done four
times after invalidate instruction cache line.

Signed-off-by: Gen Fukatsu
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-30 16:09:17 +01:00
Catalin Marinas
481467d6fa [ARM] 2939/1: Fix compilation error in arch/arm/mm/flush.c
Patch from Catalin Marinas

When CONFIG_CPU_CACHE_VIPT is defined, the flush_pfn_alias() function is
implicitely declared and it later conflicts with its actual definition.
This patch moves the function definition to the beginning of the file.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-30 16:07:04 +01:00
Russell King
840ff6a4f6 [ARM] Prevent deadlock in page fault handler
As per x86, we may deadlock while trying to get the mmap semaphore.
Implement the same fix, which allows (eg) recursive faults to cause
an oops instead of deadlocking.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-20 17:52:13 +01:00
Ben Dooks
02b7dd1244 [ARM] 2926/1: .proc.info - postfix section with .init for make buildcheck
Patch from Ben Dooks

The `make buildcheck` is erroneously reporting that the .proc.info
list is referencing items in the .init section as it is not itself
postfixed with .init

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-20 16:35:03 +01:00
Linus Torvalds
486a153f0e Merge master.kernel.org:/pub/scm/linux/kernel/git/sam/kbuild 2005-09-09 15:46:49 -07:00
Sam Ravnborg
e6ae744dd2 kbuild: arm - use generic asm-offsets.h support
Delete obsoleted stuff from arch Makefile and rename
constants.h to asm-offsets.h

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2005-09-09 21:08:59 +02:00
Russell King
d7b6b35894 [ARM] Fix ARMv6 VIPT cache >= 32K
This adds the necessary changes to ensure that we flush the
caches correctly with aliasing VIPT caches.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-08 15:32:23 +01:00
Timothy Baldwin
ca6ca91d8c [ARM] 2875/1: Data Abort fixes
Patch from Timothy Baldwin

All data aborts are treated as read accesses. The existing code updates the wrong bit of r1, also the comments are wrong in that the sense of the L bit is inverted.

Signed-off-by: Timothy E. Baldwin <T.E.Baldwin99@members.leeds.ac.uk>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-04 10:13:48 +01:00
Russell King
86a8a83963 [ARM] Fix ARMv6 page table bits
We weren't explicitly setting the page table bits we desired
in user_prot in the protection table, which resulted in the
user mappings for v6 CPUs being marked global.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-01 22:41:55 +01:00
Russell King
103461a80c [ARM] Simplify setup_mm_for_reboot()
No point checking what CPU architecture level we have each time
within the loop, so precompute the base PMD flags outside the
loop.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-01 14:51:59 +01:00
Russell King
08f4ffb3eb [ARM] Convert open-coded __pmd_populate to use inline function
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-01 14:45:18 +01:00
Steve Longerbeam
f21ee2d424 [ARM] 2867/2: unaligned ldrd/strd fixups
Patch from Steve Longerbeam

Adds an implementation of unaligned LDRD and STRD fixups.
Also fixes a bug where do_alignment() would misinterpret and
fixup an unaligned LDRD/STRD as LDRH/STRH, causing memory
corruption.
This is the same as Patch #2867/1, but with minor whitespace
and comments changes, plus a check for arch-level >= v5TE
before printing ai_dword count in proc_alignment_read().

Signed-off-by: Steve Longerbeam <stevel@mwwireless.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-31 21:22:20 +01:00
Deepak Saxena
083bc6b3c9 [ARM] 2853/1: Make alloc_init_supersection() work with 36-bit mappings
Patch from Deepak Saxena

Working on adding support for 36-bit static mappings for ARMv6 and
Intel's XSC3 core and noticed that alloc_init_supersection currently
increments the phys addr by 1MB on each of the 16 iterations and then
forces alignment to supersection size (16MB).  This is really uneeded
b/c we have already forced the phys address to be 16MB aligned in
create_mapping(). Furthermore, this breaks 36-bit addressing b/c bits
[23:20] of the PMD contain bits [35:32] of the physical address and
the masking causes us to loose those bits thus ending up with an
incorrect virt -> phys translation.  The other option is to have an
alloc_init_supersection36.
Tested on Intel IXP2350 CPU with 36-bit static I/O mappings.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-29 22:54:53 +01:00
Sean Lee
22d8be866e [ARM] 2852/1: Correct the mistake in arch/arm/mm/Kconfig file
Patch from Sean Lee

In the arch/arm/mm/Kconfig file, the CPU_DCACHE_WRITETHROUGH
option is depend on the CPU_DISABLE_DCACHE, but the "Disable
D-Cache" option is configured as CPU_DCACHE_DISABLE.
The CPU_DISABLE_DCACHE should be CPU_DCACHE_DISABLE

Signed-off-by: Sean Lee <beginner2arm@eyou.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-17 09:28:26 +01:00
Russell King
d93742f5a7 [ARM] Remove extraneous whitespace introduced in previous ARMv6 patch
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-15 16:53:38 +01:00
Russell King
6626a7076d [ARM] Control v6 'global' bit via Linux PTE entries
Unfortunately, we can't use the "user" bit in the page tables to
control whether a page table entry is "global" or "asid" specific,
since the vector page is mapped as "user" accessible but is not
process specific.

Therefore, give direct control of the ARMv6 "nG" (not global)
bit to the mm layers.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-10 16:18:35 +01:00
Russell King
1b9749e7f1 [ARM] Use #defined constants for manipulating v6 hardware PTE bits
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-10 16:15:32 +01:00
Russell King
ff2afb9df6 [PATCH] ARM: Fix ARM fault handler for get_user_pages() fixes.
The ARM fault handler is optimised to make the fast path, err, fast.
The renumbering of the VM_FAULT_* codes broke this because numbers
were used instead of the definitions.  Fix this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-04 14:17:33 +01:00
Deepak Saxena
975ad141ee [PATCH] ARM: 2839/1: Remove XScale cache and TLB locking code
Patch from Deepak Saxena

The XScale locking code is not something that has been validated
on 2.6 and needs to be replaced with a more generic API to use
with other ARMs that support locking features.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-03 19:49:17 +01:00
Russell King
186efd5275 [PATCH] ARM SMP: Mark device mappings as "device" in ARMv6 parlance
ARMv6 introduces memory types into the page tables.  Mark devices
mappings with the "shared device" memory type.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-07-26 19:51:26 +01:00
Tony Lindgren
b288f75ffa [PATCH] ARM: 2798/1: OMAP update 2/11: Change ARM Kconfig to support omap1 and omap2
Patch from Tony Lindgren

This patch by Paul Mundt and other OMAP developers modifies
ARM specific Kconfig to allow sharing code between OMAP1 and
OMAP2 architectures.
In order to share code between OMAP1 and OMAP2, all OMAP1
specific code is moved into mach-omap1 directory in the
following patch. A new mach-omap2 directory will be added
later on.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-07-10 19:58:08 +01:00
Deepak Saxena
8107338bf9 [PATCH] ARM: 2796/1: Fix ARMv5[TEJ] check in MMU initalization
Patch from Deepak Saxena

The code in mm-armv.c checks for the condition (cpu_architecture()<= ARMv5)
in a few places but should be checking for ARMv5TEJ as the MMU is shared
across all v5 variations.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-07-10 19:44:55 +01:00
Catalin Marinas
d1d890edac [PATCH] ARM: 2789/1: Enable access to both CP10 and CP11 on ARMv6
Patch from Catalin Marinas

The VFP instructions trigger undefined exceptions because the access to
CP11 is disabled (only CP10 is currently enabled by the kernel). The patch
fixes this problem.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-07-06 23:06:03 +01:00
Catalin Marinas
0d670b413f [PATCH] ARM: 2784/1: Fix the block cache flush operation range
Patch from Catalin Marinas

The range for the ARMv6 block cache operations is inclusive but the
kernel doesn't re-calculate the end address, causing a page fault when
used (this only happens with support for cache aliasing, otherwise the
blk_flush_kern_dcache_page() is not called). This patch subtracts
L1_CACHE_BYTES from the end address.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-07-03 17:53:25 +01:00
Catalin Marinas
abaf48a05a [PATCH] ARM: 2779/1: Fix the V bit setting for the ARM1020x CPUs
Patch from Catalin Marinas

This patch fixes the V bit setting for the ARM1020x processors. At
reset, this bit is automatically set to the value of the HIVECSINIT
input signal which just happened to be 1 but it is not mandatory.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-30 17:04:14 +01:00
Catalin Marinas
c19cb1df80 [PATCH] ARM: 2777/1: Fix broken comment arch/arm/mm/proc-arm1020.S
Patch from Catalin Marinas

This patch fixes a broken comment in the proc-arm1020.S file which
prevents the file compilation

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-30 17:04:13 +01:00
Russell King
cfb0810eab [PATCH] ARM: Don't try to send a signal to pid0
If we receive an unrecognised abort during boot, don't try to
send a signal to pid0, but instead report the current state.
This leads to less confusing debug reports.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-30 11:06:49 +01:00
Russell King
564c90aa07 [PATCH] ARM SMP: Use local_flush_tlb* where we really want to be local
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-28 13:46:09 +01:00
Russell King
a013053d49 [PATCH] ARM: Move memmap freeing into init.c
It doesn't make sense for this to be in mm-armv.c now that 26-bit
ARM support is no longer integrated into arch/arm.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-27 14:16:47 +01:00
Russell King
a343e6075a [PATCH] ARM: Move PGD kernel page table initialisation
It doesn't make sense to have the PGD kernel pointers initialisation
separate from the PGD user pointers, especially when we clean the
data cache over the whole range.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-27 14:08:56 +01:00
Catalin Marinas
79042f087b [PATCH] ARM: 2698/1: Enable kernel r/w access to user pages on ARMv6
Patch from Catalin Marinas

cpu_v6_set_pte() sets the kernel access rights to r/o for user
pages (L_PTE_USER) when neither L_PTE_WRITE nor L_PTE_DIRTY are
set. This causes a kernel data abort when writing the TLS value
in the 0xffff0000 page. This patch enables the kernel r/w access.

Signed-off-by: Catalin Marinas
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-24 21:27:39 +01:00
Russell King
92a8cbed29 [PATCH] ARM: Remove explicit page-alignments in memory init
Since meminfo.bank[] array contains page-aligned start/size, we
no longer need to explicitly round up/down the addresses when
converting to PFNs.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-22 21:47:25 +01:00
Wolfgang Wander
1363c3cd86 [PATCH] Avoiding mmap fragmentation
Ingo recently introduced a great speedup for allocating new mmaps using the
free_area_cache pointer which boosts the specweb SSL benchmark by 4-5% and
causes huge performance increases in thread creation.

The downside of this patch is that it does lead to fragmentation in the
mmap-ed areas (visible via /proc/self/maps), such that some applications
that work fine under 2.4 kernels quickly run out of memory on any 2.6
kernel.

The problem is twofold:

  1) the free_area_cache is used to continue a search for memory where
     the last search ended.  Before the change new areas were always
     searched from the base address on.

     So now new small areas are cluttering holes of all sizes
     throughout the whole mmap-able region whereas before small holes
     tended to close holes near the base leaving holes far from the base
     large and available for larger requests.

  2) the free_area_cache also is set to the location of the last
     munmap-ed area so in scenarios where we allocate e.g.  five regions of
     1K each, then free regions 4 2 3 in this order the next request for 1K
     will be placed in the position of the old region 3, whereas before we
     appended it to the still active region 1, placing it at the location
     of the old region 2.  Before we had 1 free region of 2K, now we only
     get two free regions of 1K -> fragmentation.

The patch addresses thes issues by introducing yet another cache descriptor
cached_hole_size that contains the largest known hole size below the
current free_area_cache.  If a new request comes in the size is compared
against the cached_hole_size and if the request can be filled with a hole
below free_area_cache the search is started from the base instead.

The results look promising: Whereas 2.6.12-rc4 fragments quickly and my
(earlier posted) leakme.c test program terminates after 50000+ iterations
with 96 distinct and fragmented maps in /proc/self/maps it performs nicely
(as expected) with thread creation, Ingo's test_str02 with 20000 threads
requires 0.7s system time.

Taking out Ingo's patch (un-patch available per request) by basically
deleting all mentions of free_area_cache from the kernel and starting the
search for new memory always at the respective bases we observe: leakme
terminates successfully with 11 distinctive hardly fragmented areas in
/proc/self/maps but thread creating is gringdingly slow: 30+s(!) system
time for Ingo's test_str02 with 20000 threads.

Now - drumroll ;-) the appended patch works fine with leakme: it ends with
only 7 distinct areas in /proc/self/maps and also thread creation seems
sufficiently fast with 0.71s for 20000 threads.

Signed-off-by: Wolfgang Wander <wwc@rentec.com>
Credit-to: "Richard Purdie" <rpurdie@rpsys.net>
Signed-off-by: Ken Chen <kenneth.w.chen@intel.com>
Acked-by: Ingo Molnar <mingo@elte.hu> (partly)
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-21 18:46:16 -07:00
Bellido Nicolas
038c5b6025 [PATCH] ARM: 2686/2: AAEC-2000 Core support
Patch from Bellido Nicolas

Core support for AAEC-2000 based platforms.
This is an updated version of the previous patch, and takes
into account Russell's comments.
AAED-2000 default configuration will follow as soon
as some problems with the bootloader are sorted out...

Signed-off-by: Nicolas Bellido
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-20 18:51:05 +01:00
Russell King
09f0551d20 [PATCH] ARM: Add iomap support for ARM
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-20 18:44:37 +01:00
Russell King
b8a9b66fbe [PATCH] ARM: Add common CACHE_COLOUR macro
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-20 11:31:09 +01:00
Russell King
8830f04a09 [PATCH] ARM: Fix delayed dcache flush for ARMv6 non-aliasing caches
flush_dcache_page() did nothing for these caches, but since they
suffer from I/D cache coherency issues, we need to ensure that data
is written back to RAM.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-20 09:51:03 +01:00
Russell King
4e71e47da3 [PATCH] ARM: Remove zero-byte sized file
Remove the remaining zero byte file left over from the Xscale
fixes.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-06-09 16:53:28 +01:00
Nicolas Pitre
dcef1f6346 [PATCH] ARM: 2664/2: add support for atomic ops on pre-ARMv6 SMP systems
Patch from Nicolas Pitre

Not that there might be many of them on the planet, but at least RMK
apparently has one.

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-08 19:00:47 +01:00
Russell King
f8f98a9335 [PATCH] ARM: Fix Xscale copy_page implementation
The ARM copypage changes in 2.6.12-rc4-git1 removed the preempt locking
from the copypage functions which broke the XScale implementation.
This patch fixes the locking on XScale and removes the now unneeded
minicache code.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
Checked-by: Richard Purdie
2005-06-08 15:28:24 +01:00
Russell King
8711a1b902 [PATCH] ARM: Fix build error
Mainline kernels don't have VECTORS_HIGH nor COPYPAGE_MINICACHE yet.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-05-16 23:36:22 +01:00
Nicolas Pitre
70489c88d0 [PATCH] ARM: 2680/1: refine TLS reg availability some more again
Patch from Nicolas Pitre

Not all ARMv6 processors implement the TLS register.

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-05-12 19:27:12 +01:00
Nicolas Pitre
fa4354359f [PATCH] ARM: 2663/2: I can't type
Patch from Nicolas Pitre

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-05-10 17:36:29 +01:00
Russell King
8d802d28c2 [PATCH] ARM: Add V6 aliasing cache flush
Add cache flushing support for aliased V6 caches to
flush_dcache_page.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-05-10 17:31:43 +01:00
Russell King
08ee4e4c5f [PATCH] ARM: Use top_pmd for V6 copy/clear user_page
Remove needless page table walking for v6 page operations.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-05-10 17:30:47 +01:00
Russell King
d2bab05ac1 [PATCH] ARM: Move copy/clear user_page locking into implementation
Move the locking for copy_user_page() and clear_user_page() into
the implementations which require locking.  For simple memcpy/
memset based implementations, the locking is extra overhead which
is not necessary, and prevents preemption occuring.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-05-10 14:23:01 +01:00
Russell King
c4e1f6f6bf [PATCH] ARM: Add top_pmd, which points at the top-most page table
Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-05-10 10:40:19 +01:00
Russell King
155bb14482 [PATCH] ARM: Add inline functions to find the pmd from virtual address
Add pmd_off() and pmd_off_k() to obtain the pmd pointer for a
virtual address, and use them throughout the mm initialisation.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-05-09 20:52:51 +01:00
Nicolas Pitre
4b0e07a556 [PATCH] ARM: 2663/1: straightify TLS register emulation a bit more
Patch from Nicolas Pitre

This better express things, and should cover RMK's weird SMP toys.

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-05-05 23:24:45 +01:00
Nicolas Pitre
48af721540 [PATCH] ARM: 2662/1: missing "default y" for CONFIG_HAS_TLS_REG
Patch from Nicolas Pitre

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-05-03 22:57:56 +01:00
George G. Davis
ca315159df [PATCH] ARM: 2656/1: Access permission bits are wrong for kernel XIP sections on ARMv6
Patch from George G. Davis

This patch is required for kernel XIP support on ARMv6 machines.  It ensures that the access permission bits for kernel XIP section descriptors are APX=1 and AP[1:0]=01, which is Kernel read-only/User no access permissions.  Prior to this change, kernel XIP section descriptor access permissions were set to Kernel no access/User no access on ARMv6 machines and the kernel would therefore hang upon entry to userspace when set_fs(USER_DS) was executed.

Signed-off-by: Steve Longerbeam
Signed-off-by: George G. Davis
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29 22:08:35 +01:00
Nicolas Pitre
2d2669b629 [PATCH] ARM: 2651/3: kernel helpers for NPTL support
Patch from Nicolas Pitre

This patch entirely reworks the kernel assistance for NPTL on ARM.
In particular this provides an efficient way to retrieve the TLS
value and perform atomic operations without any instruction emulation
nor special system call.  This even allows for pre ARMv6 binaries to
be forward compatible with SMP systems without any penalty.
The problematic and performance critical operations are performed
through segment of kernel provided user code reachable from user space
at a fixed address in kernel memory.  Those fixed entry points are
within the vector page so we basically get it for free as no extra
memory page is required and nothing else may be mapped at that
location anyway.
This is different from (but doesn't preclude) a full blown VDSO
implementation, however a VDSO would prevent some assembly tricks with
constants that allows for efficient branching to those code segments.
And since those code segments only use a few cycles before returning to
user code, the overhead of a VDSO far call would add a significant
overhead to such minimalistic operations.
The ARM_NR_set_tls syscall also changed number.  This is done for two
reasons:
1) this patch changes the way the TLS value was previously meant to be
   retrieved, therefore we ensure whatever library using the old way
   gets fixed (they only exist in private tree at the moment since the
   NPTL work is still progressing).
2) the previous number was allocated in a range causing an undefined
   instruction trap on kernels not supporting that syscall and it was
   determined that allocating it in a range returning -ENOSYS would be
   much nicer for libraries trying to determine if the feature is
   present or not.

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29 22:08:33 +01:00
George G. Davis
3a1e501511 [PATCH] ARM: 2655/1: ARM1136 SWP instruction abort handler fix
Patch from George G. Davis

As noted in http://www.arm.com/linux/patch-2.6.9-arm1.gz, the "Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR." So the v6_early_abort handler does not report the correct rd/wr direction for the SWP instruction which may result in SEGVS or hangs. In order to work around this problem, this patch merely updates the fix contained in the ARM Ltd. patch to use the macroised abort handler fixups.

Signed-off-by: George G. Davis
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29 22:08:33 +01:00
akpm@osdl.org
d42ce812b8 [PATCH] arm: add comment about max_low_pfn/max_pfn
)


From: Russell King <rmk+lkml@arm.linux.org.uk>

Oddly, max_low_pfn/max_pfn end up being the number of pages in the system,
rather than the maximum PFN on ARM.  This doesn't seem to cause any problems,
so just add a note about it.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 15:23:57 -07:00
akpm@osdl.org
2d137c24e9 [PATCH] arm: fix SIGBUS handling
)


From: Russell King <rmk+lkml@arm.linux.org.uk>

ARM wasn't raising a SIGBUS with a siginfo structure.  Fix
__do_user_fault() to allow us to use it for SIGBUS conditions, and arrange
for the sigbus path to use this.

We need to prevent the siginfo code being called if we do not have a user
space context to call it, so consolidate the "user_mode()" tests.

Thanks to Ian Campbell who spotted this oversight.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 15:23:55 -07:00
Linus Torvalds
1da177e4c3 Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!
2005-04-16 15:20:36 -07:00