[PATCH] ARM: 2651/3: kernel helpers for NPTL support
Patch from Nicolas Pitre This patch entirely reworks the kernel assistance for NPTL on ARM. In particular this provides an efficient way to retrieve the TLS value and perform atomic operations without any instruction emulation nor special system call. This even allows for pre ARMv6 binaries to be forward compatible with SMP systems without any penalty. The problematic and performance critical operations are performed through segment of kernel provided user code reachable from user space at a fixed address in kernel memory. Those fixed entry points are within the vector page so we basically get it for free as no extra memory page is required and nothing else may be mapped at that location anyway. This is different from (but doesn't preclude) a full blown VDSO implementation, however a VDSO would prevent some assembly tricks with constants that allows for efficient branching to those code segments. And since those code segments only use a few cycles before returning to user code, the overhead of a VDSO far call would add a significant overhead to such minimalistic operations. The ARM_NR_set_tls syscall also changed number. This is done for two reasons: 1) this patch changes the way the TLS value was previously meant to be retrieved, therefore we ensure whatever library using the old way gets fixed (they only exist in private tree at the moment since the NPTL work is still progressing). 2) the previous number was allocated in a range causing an undefined instruction trap on kernels not supporting that syscall and it was determined that allocating it in a range returning -ENOSYS would be much nicer for libraries trying to determine if the feature is present or not. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Nicolas Pitre
Russell King
parent
3a1e501511
commit
2d2669b629
4 changed files with 277 additions and 11 deletions
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@ -269,6 +269,12 @@ __pabt_svc:
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add r5, sp, #S_PC
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ldmia r7, {r2 - r4} @ Get USR pc, cpsr
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#if __LINUX_ARM_ARCH__ < 6
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@ make sure our user space atomic helper is aborted
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cmp r2, #VIRT_OFFSET
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bichs r3, r3, #PSR_Z_BIT
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#endif
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@
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@ We are now ready to fill in the remaining blanks on the stack:
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@
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@ -499,8 +505,12 @@ ENTRY(__switch_to)
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mra r4, r5, acc0
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stmia ip, {r4, r5}
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#endif
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#ifdef CONFIG_HAS_TLS_REG
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mcr p15, 0, r3, c13, c0, 3 @ set TLS register
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#else
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mov r4, #0xffff0fff
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str r3, [r4, #-3] @ Set TLS ptr
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str r3, [r4, #-15] @ TLS val at 0xffff0ff0
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#endif
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mcr p15, 0, r6, c3, c0, 0 @ Set domain register
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#ifdef CONFIG_VFP
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@ Always disable VFP so we can lazily save/restore the old
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@ -519,6 +529,207 @@ ENTRY(__switch_to)
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ldmib r2, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
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__INIT
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/*
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* User helpers.
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*
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* These are segment of kernel provided user code reachable from user space
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* at a fixed address in kernel memory. This is used to provide user space
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* with some operations which require kernel help because of unimplemented
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* native feature and/or instructions in many ARM CPUs. The idea is for
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* this code to be executed directly in user mode for best efficiency but
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* which is too intimate with the kernel counter part to be left to user
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* libraries. In fact this code might even differ from one CPU to another
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* depending on the available instruction set and restrictions like on
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* SMP systems. In other words, the kernel reserves the right to change
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* this code as needed without warning. Only the entry points and their
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* results are guaranteed to be stable.
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*
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* Each segment is 32-byte aligned and will be moved to the top of the high
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* vector page. New segments (if ever needed) must be added in front of
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* existing ones. This mechanism should be used only for things that are
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* really small and justified, and not be abused freely.
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*
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* User space is expected to implement those things inline when optimizing
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* for a processor that has the necessary native support, but only if such
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* resulting binaries are already to be incompatible with earlier ARM
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* processors due to the use of unsupported instructions other than what
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* is provided here. In other words don't make binaries unable to run on
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* earlier processors just for the sake of not using these kernel helpers
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* if your compiled code is not going to use the new instructions for other
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* purpose.
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*/
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.align 5
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.globl __kuser_helper_start
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__kuser_helper_start:
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/*
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* Reference prototype:
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*
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* int __kernel_cmpxchg(int oldval, int newval, int *ptr)
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*
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* Input:
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*
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* r0 = oldval
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* r1 = newval
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* r2 = ptr
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* lr = return address
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*
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* Output:
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*
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* r0 = returned value (zero or non-zero)
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* C flag = set if r0 == 0, clear if r0 != 0
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*
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* Clobbered:
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*
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* r3, ip, flags
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*
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* Definition and user space usage example:
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*
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* typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
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* #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
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*
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* Atomically store newval in *ptr if *ptr is equal to oldval for user space.
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* Return zero if *ptr was changed or non-zero if no exchange happened.
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* The C flag is also set if *ptr was changed to allow for assembly
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* optimization in the calling code.
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*
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* For example, a user space atomic_add implementation could look like this:
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*
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* #define atomic_add(ptr, val) \
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* ({ register unsigned int *__ptr asm("r2") = (ptr); \
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* register unsigned int __result asm("r1"); \
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* asm volatile ( \
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* "1: @ atomic_add\n\t" \
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* "ldr r0, [r2]\n\t" \
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* "mov r3, #0xffff0fff\n\t" \
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* "add lr, pc, #4\n\t" \
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* "add r1, r0, %2\n\t" \
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* "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
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* "bcc 1b" \
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* : "=&r" (__result) \
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* : "r" (__ptr), "rIL" (val) \
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* : "r0","r3","ip","lr","cc","memory" ); \
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* __result; })
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*/
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__kuser_cmpxchg: @ 0xffff0fc0
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#if __LINUX_ARM_ARCH__ < 6
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#ifdef CONFIG_SMP /* sanity check */
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#error "CONFIG_SMP on a machine supporting pre-ARMv6 processors?"
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#endif
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/*
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* Theory of operation:
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*
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* We set the Z flag before loading oldval. If ever an exception
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* occurs we can not be sure the loaded value will still be the same
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* when the exception returns, therefore the user exception handler
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* will clear the Z flag whenever the interrupted user code was
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* actually from the kernel address space (see the usr_entry macro).
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*
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* The post-increment on the str is used to prevent a race with an
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* exception happening just after the str instruction which would
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* clear the Z flag although the exchange was done.
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*/
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teq ip, ip @ set Z flag
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ldr ip, [r2] @ load current val
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add r3, r2, #1 @ prepare store ptr
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teqeq ip, r0 @ compare with oldval if still allowed
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streq r1, [r3, #-1]! @ store newval if still allowed
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subs r0, r2, r3 @ if r2 == r3 the str occured
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mov pc, lr
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#else
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ldrex r3, [r2]
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subs r3, r3, r0
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strexeq r3, r1, [r2]
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rsbs r0, r3, #0
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mov pc, lr
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#endif
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.align 5
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/*
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* Reference prototype:
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*
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* int __kernel_get_tls(void)
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*
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* Input:
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*
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* lr = return address
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*
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* Output:
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*
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* r0 = TLS value
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*
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* Clobbered:
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*
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* the Z flag might be lost
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*
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* Definition and user space usage example:
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*
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* typedef int (__kernel_get_tls_t)(void);
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* #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
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*
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* Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
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*
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* This could be used as follows:
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*
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* #define __kernel_get_tls() \
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* ({ register unsigned int __val asm("r0"); \
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* asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
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* : "=r" (__val) : : "lr","cc" ); \
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* __val; })
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*/
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__kuser_get_tls: @ 0xffff0fe0
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#ifndef CONFIG_HAS_TLS_REG
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#ifdef CONFIG_SMP /* sanity check */
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#error "CONFIG_SMP without CONFIG_HAS_TLS_REG is wrong"
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#endif
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ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
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mov pc, lr
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#else
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mrc p15, 0, r0, c13, c0, 3 @ read TLS register
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mov pc, lr
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#endif
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.rep 5
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.word 0 @ pad up to __kuser_helper_version
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.endr
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/*
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* Reference declaration:
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*
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* extern unsigned int __kernel_helper_version;
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*
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* Definition and user space usage example:
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*
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* #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
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*
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* User space may read this to determine the curent number of helpers
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* available.
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*/
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__kuser_helper_version: @ 0xffff0ffc
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.word ((__kuser_helper_end - __kuser_helper_start) >> 5)
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.globl __kuser_helper_end
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__kuser_helper_end:
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/*
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* Vector stubs.
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*
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@ -450,13 +450,17 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
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case NR(set_tls):
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thread->tp_value = regs->ARM_r0;
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#ifdef CONFIG_HAS_TLS_REG
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asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) );
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#else
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/*
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* Our user accessible TLS ptr is located at 0xffff0ffc.
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* On SMP read access to this address must raise a fault
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* and be emulated from the data abort handler.
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* m
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* User space must never try to access this directly.
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* Expect your app to break eventually if you do so.
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* The user helper at 0xffff0fe0 must be used instead.
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* (see entry-armv.S for details)
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*/
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*((unsigned long *)0xffff0ffc) = thread->tp_value;
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*((unsigned int *)0xffff0ff0) = regs->ARM_r0;
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#endif
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return 0;
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default:
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@ -493,6 +497,41 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
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return 0;
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}
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#if defined(CONFIG_CPU_32v6) && !defined(CONFIG_HAS_TLS_REG)
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/*
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* We might be running on an ARMv6+ processor which should have the TLS
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* register, but for some reason we can't use it and have to emulate it.
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*/
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static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
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{
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int reg = (instr >> 12) & 15;
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if (reg == 15)
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return 1;
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regs->uregs[reg] = current_thread_info()->tp_value;
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regs->ARM_pc += 4;
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return 0;
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}
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static struct undef_hook arm_mrc_hook = {
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.instr_mask = 0x0fff0fff,
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.instr_val = 0x0e1d0f70,
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.cpsr_mask = PSR_T_BIT,
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.cpsr_val = 0,
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.fn = get_tp_trap,
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};
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static int __init arm_mrc_hook_init(void)
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{
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register_undef_hook(&arm_mrc_hook);
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return 0;
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}
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late_initcall(arm_mrc_hook_init);
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#endif
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void __bad_xchg(volatile void *ptr, int size)
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{
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printk("xchg: bad data size: pc 0x%p, ptr 0x%p, size %d\n",
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@ -580,14 +619,17 @@ void __init trap_init(void)
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{
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extern char __stubs_start[], __stubs_end[];
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extern char __vectors_start[], __vectors_end[];
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extern char __kuser_helper_start[], __kuser_helper_end[];
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int kuser_sz = __kuser_helper_end - __kuser_helper_start;
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/*
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* Copy the vectors and stubs (in entry-armv.S) into the
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* vector page, mapped at 0xffff0000, and ensure these are
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* visible to the instruction stream.
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* Copy the vectors, stubs and kuser helpers (in entry-armv.S)
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* into the vector page, mapped at 0xffff0000, and ensure these
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* are visible to the instruction stream.
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*/
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memcpy((void *)0xffff0000, __vectors_start, __vectors_end - __vectors_start);
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memcpy((void *)0xffff0200, __stubs_start, __stubs_end - __stubs_start);
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memcpy((void *)0xffff1000 - kuser_sz, __kuser_helper_start, kuser_sz);
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flush_icache_range(0xffff0000, 0xffff0000 + PAGE_SIZE);
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modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
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}
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@ -409,3 +409,17 @@ config CPU_BPREDICT_DISABLE
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depends on CPU_ARM1020
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help
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Say Y here to disable branch prediction. If unsure, say N.
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config HAS_TLS_REG
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bool
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depends on CPU_32v6 && !CPU_32v5 && !CPU_32v4 && !CPU_32v3
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help
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This selects support for the CP15 thread register.
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It is defined to be available on ARMv6 or later. However
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if the kernel is configured to support multiple CPUs including
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a pre-ARMv6 processors, or if a given ARMv6 processor doesn't
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implement the thread register for some reason, then access to
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this register from user space must be trapped and emulated.
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If user space is relying on the __kuser_get_tls code then
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there should not be any impact.
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@ -359,8 +359,7 @@
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#define __ARM_NR_cacheflush (__ARM_NR_BASE+2)
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#define __ARM_NR_usr26 (__ARM_NR_BASE+3)
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#define __ARM_NR_usr32 (__ARM_NR_BASE+4)
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#define __ARM_NR_set_tls (__ARM_NR_BASE+0x800)
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#define __ARM_NR_set_tls (__ARM_NR_BASE+5)
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#define __sys2(x) #x
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#define __sys1(x) __sys2(x)
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