fcb243918f
Looks like the copying of MMR defines from the SDH block missed updating the addresses of the RSI_PID# registers. So tweak them to reflect the actual hardware. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
48 lines
2.8 KiB
C
48 lines
2.8 KiB
C
/*
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* Copyright 2008-2009 Analog Devices Inc.
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*
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* Licensed under the ADI BSD license or the GPL-2 (or later)
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*/
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#ifndef _DEF_BF514_H
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#define _DEF_BF514_H
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/* BF514 is BF512 + RSI */
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#include "defBF512.h"
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/* Removable Storage Interface Registers */
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#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
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#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
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#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
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#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
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#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
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#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
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#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
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#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
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#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
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#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
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#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
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#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
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#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
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#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
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#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
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#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
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#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
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#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
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#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
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#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
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#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
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#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
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#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
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#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
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#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
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#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
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#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
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#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
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#define RSI_PID4 0xFFC038E0 /* RSI Peripheral ID Register 0 */
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#define RSI_PID5 0xFFC038E4 /* RSI Peripheral ID Register 1 */
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#define RSI_PID6 0xFFC038E8 /* RSI Peripheral ID Register 2 */
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#define RSI_PID7 0xFFC038EC /* RSI Peripheral ID Register 3 */
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#endif /* _DEF_BF514_H */
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