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Blackfin: bf51x: fix up RSI_PID# MMR defines

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Looks like the copying of MMR defines from the SDH block missed updating
the addresses of the RSI_PID# registers.  So tweak them to reflect the
actual hardware.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2011-05-26 18:05:15 -04:00
parent 61aa818f7b
commit fcb243918f
1 changed files with 8 additions and 8 deletions
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16
arch/blackfin/mach-bf518/include/mach/defBF514.h
View file

@ -36,13 +36,13 @@
#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
#define RSI_PID4 0xFFC038E0 /* RSI Peripheral ID Register 0 */
#define RSI_PID5 0xFFC038E4 /* RSI Peripheral ID Register 1 */
#define RSI_PID6 0xFFC038E8 /* RSI Peripheral ID Register 2 */
#define RSI_PID7 0xFFC038EC /* RSI Peripheral ID Register 3 */
#endif /* _DEF_BF514_H */