5566cb7c91
Now, memory size is properly displayed: EDAC i7core: DOD Max limits: DIMMS: 2, 1-ranked, 8-banked EDAC i7core: DOD Max rows x colums = 0x4000 x 0x400 EDAC i7core: Memory channel configuration: EDAC i7core: Ch0 phy rd0, wr0 (0x063f7c31): 2 ranks, UDIMMs EDAC i7core: dimm 0 (0x00000288) 1024 Mb offset: 0, numbank: 8, numrank: 1, numrow: 0x4000, numcol: 0x400 EDAC i7core: dimm 1 (0x00001288) 1024 Mb offset: 4, numbank: 8, numrank: 1, numrow: 0x4000, numcol: 0x400 EDAC i7core: Ch1 phy rd1, wr1 (0x063f7c31): 2 ranks, UDIMMs EDAC i7core: dimm 0 (0x00000288) 1024 Mb offset: 0, numbank: 8, numrank: 1, numrow: 0x4000, numcol: 0x400 EDAC i7core: Ch2 phy rd3, wr3 (0x063f7c31): 2 ranks, UDIMMs EDAC i7core: dimm 0 (0x00000288) 1024 Mb offset: 0, numbank: 8, numrank: 1, numrow: 0x4000, numcol: 0x400 Still, as the way to retrieve csrows info is not known, it does a mapping of what's available to csrows basic unit at edac core. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> |
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.. | ||
amd64_edac.c | ||
amd64_edac.h | ||
amd64_edac_dbg.c | ||
amd64_edac_inj.c | ||
amd76x_edac.c | ||
amd8111_edac.c | ||
amd8111_edac.h | ||
amd8131_edac.c | ||
amd8131_edac.h | ||
cell_edac.c | ||
cpc925_edac.c | ||
e7xxx_edac.c | ||
e752x_edac.c | ||
edac_core.h | ||
edac_device.c | ||
edac_device_sysfs.c | ||
edac_mc.c | ||
edac_mc_sysfs.c | ||
edac_mce_amd.c | ||
edac_mce_amd.h | ||
edac_module.c | ||
edac_module.h | ||
edac_pci.c | ||
edac_pci_sysfs.c | ||
edac_stub.c | ||
i7core_edac.c | ||
i3000_edac.c | ||
i3200_edac.c | ||
i5000_edac.c | ||
i5100_edac.c | ||
i5400_edac.c | ||
i82443bxgx_edac.c | ||
i82860_edac.c | ||
i82875p_edac.c | ||
i82975x_edac.c | ||
Kconfig | ||
Makefile | ||
mpc85xx_edac.c | ||
mpc85xx_edac.h | ||
mv64x60_edac.c | ||
mv64x60_edac.h | ||
pasemi_edac.c | ||
ppc4xx_edac.c | ||
ppc4xx_edac.h | ||
r82600_edac.c | ||
x38_edac.c |