x86, mce: pass mce info to EDAC for decoding
Move NB decoder along with required defines to EDAC MCE core. Add registration routines for further decoding of the MCE info in the AMD64 EDAC module. CC: Andi Kleen <andi@firstfloor.org> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov
parent
ecaf5606de
commit
549d042df2
6 changed files with 185 additions and 111 deletions
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@ -183,6 +183,11 @@ void mce_log(struct mce *mce)
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set_bit(0, &mce_need_notify);
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}
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void __weak decode_mce(struct mce *m)
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{
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return;
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}
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static void print_mce(struct mce *m)
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{
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printk(KERN_EMERG
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@ -205,6 +210,8 @@ static void print_mce(struct mce *m)
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printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
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m->cpuvendor, m->cpuid, m->time, m->socketid,
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m->apicid);
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decode_mce(m);
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}
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static void print_mce_head(void)
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@ -2282,8 +2282,8 @@ static void amd64_handle_ue(struct mem_ctl_info *mci,
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}
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}
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static void amd64_decode_bus_error(struct mem_ctl_info *mci,
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struct err_regs *info, int ecc_type)
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static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
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struct err_regs *info, int ecc_type)
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{
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u32 ec = ERROR_CODE(info->nbsl);
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u32 xec = EXT_ERROR_CODE(info->nbsl);
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@ -2316,86 +2316,23 @@ static void amd64_decode_bus_error(struct mem_ctl_info *mci,
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edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR "Error Overflow");
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}
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void amd64_decode_nb_mce(struct mem_ctl_info *mci, struct err_regs *regs,
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int handle_errors)
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void amd64_decode_bus_error(int node_id, struct err_regs *regs,
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int ecc_type)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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int ecc;
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u32 ec = ERROR_CODE(regs->nbsl);
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u32 xec = EXT_ERROR_CODE(regs->nbsl);
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struct mem_ctl_info *mci = mci_lookup[node_id];
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if (!handle_errors)
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return;
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pr_emerg(" Northbridge ERROR, mc node %d", pvt->mc_node_id);
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/*
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* F10h, revD can disable ErrCpu[3:0] so check that first and also the
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* value encoding has changed so interpret those differently
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*/
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if ((boot_cpu_data.x86 == 0x10) &&
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(boot_cpu_data.x86_model > 8)) {
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if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
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pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
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} else {
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pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf)));
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}
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pr_emerg(" Error: %sorrected",
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((regs->nbsh & K8_NBSH_UC_ERR) ? "Unc" : "C"));
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pr_cont(", Report Error: %s",
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((regs->nbsh & K8_NBSH_ERR_EN) ? "yes" : "no"));
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pr_cont(", MiscV: %svalid, CPU context corrupt: %s",
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((regs->nbsh & K8_NBSH_MISCV) ? "" : "In"),
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((regs->nbsh & K8_NBSH_PCC) ? "yes" : "no"));
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/* do the two bits[14:13] together */
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ecc = regs->nbsh & (0x3 << 13);
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if (ecc)
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pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));
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pr_cont("\n");
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if (TLB_ERROR(ec)) {
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/*
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* GART errors are intended to help graphics driver developers
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* to detect bad GART PTEs. It is recommended by AMD to disable
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* GART table walk error reporting by default[1] (currently
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* being disabled in mce_cpu_quirks()) and according to the
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* comment in mce_cpu_quirks(), such GART errors can be
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* incorrectly triggered. We may see these errors anyway and
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* unless requested by the user, they won't be reported.
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*
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* [1] section 13.10.1 on BIOS and Kernel Developers Guide for
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* AMD NPT family 0Fh processors
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*/
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if (!report_gart_errors)
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return;
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pr_emerg(" GART TLB error, Transaction: %s, Cache Level %s\n",
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TT_MSG(ec), LL_MSG(ec));
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} else if (MEM_ERROR(ec)) {
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pr_emerg(" Memory/Cache error, Transaction: %s, Type: %s,"
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" Cache Level: %s",
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RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
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} else if (BUS_ERROR(ec)) {
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pr_emerg(" Bus (Link/DRAM) error\n");
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amd64_decode_bus_error(mci, regs, ecc);
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} else {
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/* shouldn't reach here! */
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amd64_mc_printk(mci, KERN_WARNING,
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"%s(): unknown MCE error 0x%x\n", __func__, ec);
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}
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pr_emerg("%s.\n", EXT_ERR_MSG(xec));
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__amd64_decode_bus_error(mci, regs, ecc_type);
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/*
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* Check the UE bit of the NB status high register, if set generate some
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* logs. If NOT a GART error, then process the event as a NO-INFO event.
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* If it was a GART error, skip that process.
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*
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* FIXME: this should go somewhere else, if at all.
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*/
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if (regs->nbsh & K8_NBSH_UC_ERR && !report_gart_errors)
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edac_mc_handle_ue_no_info(mci, "UE bit is set");
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}
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/*
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@ -2406,8 +2343,10 @@ static void amd64_check(struct mem_ctl_info *mci)
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{
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struct err_regs regs;
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if (amd64_get_error_info(mci, ®s))
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amd64_decode_nb_mce(mci, ®s, 1);
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if (amd64_get_error_info(mci, ®s)) {
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struct amd64_pvt *pvt = mci->pvt_info;
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amd_decode_nb_mce(pvt->mc_node_id, ®s, 1);
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}
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}
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/*
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@ -3103,6 +3042,13 @@ static int amd64_init_2nd_stage(struct amd64_pvt *pvt)
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mci_lookup[node_id] = mci;
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pvt_lookup[node_id] = NULL;
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/* register stuff with EDAC MCE */
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if (report_gart_errors)
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amd_report_gart_errors(true);
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amd_register_ecc_decoder(amd64_decode_bus_error);
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return 0;
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err_add_mc:
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@ -3169,6 +3115,10 @@ static void __devexit amd64_remove_one_instance(struct pci_dev *pdev)
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mci_lookup[pvt->mc_node_id] = NULL;
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/* unregister from EDAC MCE */
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amd_report_gart_errors(false);
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amd_unregister_ecc_decoder(amd64_decode_bus_error);
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/* Free the EDAC CORE resources */
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edac_mc_free(mci);
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}
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@ -346,24 +346,8 @@ enum {
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#define K8_NBSL_PP_OBS 0x2
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#define K8_NBSL_PP_GENERIC 0x3
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#define K8_NBSH 0x4C
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#define K8_NBSH_VALID_BIT BIT(31)
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#define K8_NBSH_OVERFLOW BIT(30)
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#define K8_NBSH_UC_ERR BIT(29)
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#define K8_NBSH_ERR_EN BIT(28)
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#define K8_NBSH_MISCV BIT(27)
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#define K8_NBSH_VALID_ERROR_ADDR BIT(26)
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#define K8_NBSH_PCC BIT(25)
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#define K8_NBSH_ERR_CPU_VAL BIT(24)
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#define K8_NBSH_CECC BIT(14)
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#define K8_NBSH_UECC BIT(13)
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#define K8_NBSH_ERR_SCRUBER BIT(8)
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#define EXTRACT_ERR_CPU_MAP(x) ((x) & 0xF)
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#define K8_NBEAL 0x50
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#define K8_NBEAH 0x54
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#define K8_SCRCTRL 0x58
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@ -428,23 +412,6 @@ enum amd64_chipset_families {
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F11_CPUS,
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};
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/*
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* Structure to hold:
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*
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* 1) dynamically read status and error address HW registers
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* 2) sysfs entered values
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* 3) MCE values
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*
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* Depends on entry into the modules
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*/
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struct err_regs {
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u32 nbcfg;
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u32 nbsh;
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u32 nbsl;
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u32 nbeah;
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u32 nbeal;
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};
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/* Error injection control structure */
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struct error_injection {
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u32 section;
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@ -610,8 +577,5 @@ static inline struct low_ops *family_ops(int index)
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#define F10_MIN_SCRUB_RATE_BITS 0x5
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#define F11_MIN_SCRUB_RATE_BITS 0x6
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void amd64_decode_nb_mce(struct mem_ctl_info *mci, struct err_regs *info,
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int handle_errors);
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int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
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u64 *hole_offset, u64 *hole_size);
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@ -24,7 +24,7 @@ static ssize_t amd64_nbea_store(struct mem_ctl_info *mci, const char *data,
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/* Process the Mapping request */
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/* TODO: Add race prevention */
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amd64_decode_nb_mce(mci, &pvt->ctl_error_info, 1);
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amd_decode_nb_mce(pvt->mc_node_id, &pvt->ctl_error_info, 1);
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return count;
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}
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@ -1,6 +1,31 @@
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#include <linux/module.h>
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#include "edac_mce_amd.h"
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static bool report_gart_errors;
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static void (*nb_bus_decoder)(int node_id, struct err_regs *regs, int ecc_type);
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void amd_report_gart_errors(bool v)
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{
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report_gart_errors = v;
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}
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EXPORT_SYMBOL_GPL(amd_report_gart_errors);
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void amd_register_ecc_decoder(void (*f)(int, struct err_regs *, int))
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{
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nb_bus_decoder = f;
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}
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EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
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void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *, int))
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{
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if (nb_bus_decoder) {
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WARN_ON(nb_bus_decoder != f);
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nb_bus_decoder = NULL;
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}
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}
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EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
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/*
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* string representation for the different MCA reported error types, see F3x48
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* or MSR0000_0411.
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@ -102,3 +127,93 @@ const char *ext_msgs[] = {
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"Probe Filter error" /* 1_1111b */
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};
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EXPORT_SYMBOL_GPL(ext_msgs);
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void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
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{
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int ecc;
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u32 ec = ERROR_CODE(regs->nbsl);
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u32 xec = EXT_ERROR_CODE(regs->nbsl);
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if (!handle_errors)
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return;
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pr_emerg(" Northbridge Error, node %d", node_id);
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/*
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* F10h, revD can disable ErrCpu[3:0] so check that first and also the
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* value encoding has changed so interpret those differently
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*/
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if ((boot_cpu_data.x86 == 0x10) &&
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(boot_cpu_data.x86_model > 8)) {
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if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
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pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
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} else {
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pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf)));
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}
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pr_emerg(" Error: %sorrected",
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((regs->nbsh & K8_NBSH_UC_ERR) ? "Unc" : "C"));
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pr_cont(", Report Error: %s",
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((regs->nbsh & K8_NBSH_ERR_EN) ? "yes" : "no"));
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pr_cont(", MiscV: %svalid, CPU context corrupt: %s",
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((regs->nbsh & K8_NBSH_MISCV) ? "" : "In"),
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((regs->nbsh & K8_NBSH_PCC) ? "yes" : "no"));
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/* do the two bits[14:13] together */
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ecc = regs->nbsh & (0x3 << 13);
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if (ecc)
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pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));
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pr_cont("\n");
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if (TLB_ERROR(ec)) {
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/*
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* GART errors are intended to help graphics driver developers
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* to detect bad GART PTEs. It is recommended by AMD to disable
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* GART table walk error reporting by default[1] (currently
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* being disabled in mce_cpu_quirks()) and according to the
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* comment in mce_cpu_quirks(), such GART errors can be
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* incorrectly triggered. We may see these errors anyway and
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* unless requested by the user, they won't be reported.
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*
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* [1] section 13.10.1 on BIOS and Kernel Developers Guide for
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* AMD NPT family 0Fh processors
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*/
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if (!report_gart_errors)
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return;
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pr_emerg(" GART TLB error, Transaction: %s, Cache Level %s\n",
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TT_MSG(ec), LL_MSG(ec));
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} else if (MEM_ERROR(ec)) {
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pr_emerg(" Memory/Cache error, Transaction: %s, Type: %s,"
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" Cache Level: %s",
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RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
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} else if (BUS_ERROR(ec)) {
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pr_emerg(" Bus (Link/DRAM) error\n");
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if (nb_bus_decoder)
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nb_bus_decoder(node_id, regs, ecc);
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} else {
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/* shouldn't reach here! */
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pr_warning("%s: unknown MCE error 0x%x\n", __func__, ec);
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}
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pr_emerg("%s.\n", EXT_ERR_MSG(xec));
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}
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EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
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void decode_mce(struct mce *m)
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{
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struct err_regs regs;
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int node;
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if (m->bank != 4)
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return;
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regs.nbsl = (u32) m->status;
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regs.nbsh = (u32)(m->status >> 32);
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regs.nbeal = (u32) m->addr;
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regs.nbeah = (u32)(m->addr >> 32);
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node = topology_cpu_node_id(m->extcpu);
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amd_decode_nb_mce(node, ®s, 1);
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}
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@ -1,3 +1,8 @@
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#ifndef _EDAC_MCE_AMD_H
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#define _EDAC_MCE_AMD_H
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#include <asm/mce.h>
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#define ERROR_CODE(x) ((x) & 0xffff)
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#define EXT_ERROR_CODE(x) (((x) >> 16) & 0x1f)
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#define EXT_ERR_MSG(x) ext_msgs[EXT_ERROR_CODE(x)]
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@ -22,6 +27,20 @@
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#define PP(x) (((x) >> 9) & 0x3)
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#define PP_MSG(x) pp_msgs[PP(x)]
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#define K8_NBSH 0x4C
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#define K8_NBSH_VALID_BIT BIT(31)
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#define K8_NBSH_OVERFLOW BIT(30)
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#define K8_NBSH_UC_ERR BIT(29)
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#define K8_NBSH_ERR_EN BIT(28)
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#define K8_NBSH_MISCV BIT(27)
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#define K8_NBSH_VALID_ERROR_ADDR BIT(26)
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#define K8_NBSH_PCC BIT(25)
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#define K8_NBSH_ERR_CPU_VAL BIT(24)
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#define K8_NBSH_CECC BIT(14)
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#define K8_NBSH_UECC BIT(13)
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#define K8_NBSH_ERR_SCRUBER BIT(8)
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extern const char *tt_msgs[];
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extern const char *ll_msgs[];
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extern const char *rrrr_msgs[];
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@ -29,3 +48,22 @@ extern const char *pp_msgs[];
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extern const char *to_msgs[];
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extern const char *ii_msgs[];
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extern const char *ext_msgs[];
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/*
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* relevant NB regs
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*/
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struct err_regs {
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u32 nbcfg;
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u32 nbsh;
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u32 nbsl;
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u32 nbeah;
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u32 nbeal;
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};
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void amd_report_gart_errors(bool);
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void amd_register_ecc_decoder(void (*f)(int, struct err_regs *, int));
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void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *, int));
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void amd_decode_nb_mce(int, struct err_regs *, int);
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#endif /* _EDAC_MCE_AMD_H */
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