bda0030366
Add a the common code used by all PXA variants. This is the first step in the transition from architecture defined clocks (in arch/arm/mach-pxa) towards clock framework. The goal is to have the same features (and not all the features) of the existing clocks, and enable the transition of PXA to device-tree. All PXA rely on a "CKEN" type clock, which : - has a gate (bit in CKEN register) - is generated from a PLL, generally divided - has an alternate low power clock Each variant will specialize the CKEN clock : - pxa25x have no low power clock - pxa27x in low power use always the 13 MHz ring oscillator - pxa3xx in low power have specific dividers for each clock The device-tree provides a list of CLK_* (ex: CLK_USB or CLK_I2C) to get a handle on the clock. While pxa-clock.h will describe all the clocks of all the variants, each variant will only use a subset of it. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org>
97 lines
2.4 KiB
C
97 lines
2.4 KiB
C
/*
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* Marvell PXA family clocks
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*
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* Copyright (C) 2014 Robert Jarzmik
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*
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* Common clock code for PXA clocks ("CKEN" type clocks + DT)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/pxa-clock.h>
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#include "clk-pxa.h"
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DEFINE_SPINLOCK(lock);
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static struct clk *pxa_clocks[CLK_MAX];
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static struct clk_onecell_data onecell_data = {
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.clks = pxa_clocks,
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.clk_num = CLK_MAX,
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};
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#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk_cken, hw)
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static unsigned long cken_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct pxa_clk_cken *pclk = to_pxa_clk(hw);
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struct clk_fixed_factor *fix;
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if (!pclk->is_in_low_power || pclk->is_in_low_power())
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fix = &pclk->lp;
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else
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fix = &pclk->hp;
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fix->hw.clk = hw->clk;
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return clk_fixed_factor_ops.recalc_rate(&fix->hw, parent_rate);
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}
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static struct clk_ops cken_rate_ops = {
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.recalc_rate = cken_recalc_rate,
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};
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static u8 cken_get_parent(struct clk_hw *hw)
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{
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struct pxa_clk_cken *pclk = to_pxa_clk(hw);
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if (!pclk->is_in_low_power)
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return 0;
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return pclk->is_in_low_power() ? 0 : 1;
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}
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static struct clk_ops cken_mux_ops = {
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.get_parent = cken_get_parent,
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.set_parent = dummy_clk_set_parent,
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};
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void __init clkdev_pxa_register(int ckid, const char *con_id,
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const char *dev_id, struct clk *clk)
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{
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if (!IS_ERR(clk) && (ckid != CLK_NONE))
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pxa_clocks[ckid] = clk;
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if (!IS_ERR(clk))
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clk_register_clkdev(clk, con_id, dev_id);
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}
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int __init clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks)
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{
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int i;
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struct pxa_clk_cken *pclk;
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struct clk *clk;
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for (i = 0; i < nb_clks; i++) {
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pclk = clks + i;
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pclk->gate.lock = &lock;
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clk = clk_register_composite(NULL, pclk->name,
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pclk->parent_names, 2,
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&pclk->hw, &cken_mux_ops,
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&pclk->hw, &cken_rate_ops,
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&pclk->gate.hw, &clk_gate_ops,
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pclk->flags);
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clkdev_pxa_register(pclk->ckid, pclk->con_id, pclk->dev_id,
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clk);
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}
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return 0;
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}
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static void __init pxa_dt_clocks_init(struct device_node *np)
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{
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of_clk_add_provider(np, of_clk_src_onecell_get, &onecell_data);
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}
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CLK_OF_DECLARE(pxa_clks, "marvell,pxa-clocks", pxa_dt_clocks_init);
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