clk: add pxa clocks infrastructure
Add a the common code used by all PXA variants. This is the first step in the transition from architecture defined clocks (in arch/arm/mach-pxa) towards clock framework. The goal is to have the same features (and not all the features) of the existing clocks, and enable the transition of PXA to device-tree. All PXA rely on a "CKEN" type clock, which : - has a gate (bit in CKEN register) - is generated from a PLL, generally divided - has an alternate low power clock Each variant will specialize the CKEN clock : - pxa25x have no low power clock - pxa27x in low power use always the 13 MHz ring oscillator - pxa3xx in low power have specific dividers for each clock The device-tree provides a list of CLK_* (ex: CLK_USB or CLK_I2C) to get a handle on the clock. While pxa-clock.h will describe all the clocks of all the variants, each variant will only use a subset of it. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Robert Jarzmik
Mike Turquette
parent
7d1311b93e
commit
bda0030366
5 changed files with 283 additions and 0 deletions
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@ -48,6 +48,7 @@ obj-$(CONFIG_ARCH_MMP) += mmp/
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endif
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obj-$(CONFIG_PLAT_ORION) += mvebu/
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obj-$(CONFIG_ARCH_MXS) += mxs/
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obj-$(CONFIG_ARCH_PXA) += pxa/
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obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
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1
drivers/clk/pxa/Makefile
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1
drivers/clk/pxa/Makefile
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@ -0,0 +1 @@
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obj-y += clk-pxa.o
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97
drivers/clk/pxa/clk-pxa.c
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97
drivers/clk/pxa/clk-pxa.c
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@ -0,0 +1,97 @@
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/*
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* Marvell PXA family clocks
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*
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* Copyright (C) 2014 Robert Jarzmik
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*
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* Common clock code for PXA clocks ("CKEN" type clocks + DT)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/pxa-clock.h>
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#include "clk-pxa.h"
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DEFINE_SPINLOCK(lock);
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static struct clk *pxa_clocks[CLK_MAX];
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static struct clk_onecell_data onecell_data = {
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.clks = pxa_clocks,
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.clk_num = CLK_MAX,
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};
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#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk_cken, hw)
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static unsigned long cken_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct pxa_clk_cken *pclk = to_pxa_clk(hw);
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struct clk_fixed_factor *fix;
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if (!pclk->is_in_low_power || pclk->is_in_low_power())
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fix = &pclk->lp;
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else
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fix = &pclk->hp;
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fix->hw.clk = hw->clk;
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return clk_fixed_factor_ops.recalc_rate(&fix->hw, parent_rate);
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}
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static struct clk_ops cken_rate_ops = {
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.recalc_rate = cken_recalc_rate,
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};
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static u8 cken_get_parent(struct clk_hw *hw)
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{
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struct pxa_clk_cken *pclk = to_pxa_clk(hw);
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if (!pclk->is_in_low_power)
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return 0;
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return pclk->is_in_low_power() ? 0 : 1;
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}
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static struct clk_ops cken_mux_ops = {
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.get_parent = cken_get_parent,
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.set_parent = dummy_clk_set_parent,
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};
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void __init clkdev_pxa_register(int ckid, const char *con_id,
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const char *dev_id, struct clk *clk)
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{
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if (!IS_ERR(clk) && (ckid != CLK_NONE))
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pxa_clocks[ckid] = clk;
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if (!IS_ERR(clk))
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clk_register_clkdev(clk, con_id, dev_id);
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}
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int __init clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks)
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{
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int i;
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struct pxa_clk_cken *pclk;
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struct clk *clk;
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for (i = 0; i < nb_clks; i++) {
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pclk = clks + i;
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pclk->gate.lock = &lock;
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clk = clk_register_composite(NULL, pclk->name,
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pclk->parent_names, 2,
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&pclk->hw, &cken_mux_ops,
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&pclk->hw, &cken_rate_ops,
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&pclk->gate.hw, &clk_gate_ops,
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pclk->flags);
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clkdev_pxa_register(pclk->ckid, pclk->con_id, pclk->dev_id,
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clk);
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}
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return 0;
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}
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static void __init pxa_dt_clocks_init(struct device_node *np)
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{
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of_clk_add_provider(np, of_clk_src_onecell_get, &onecell_data);
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}
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CLK_OF_DECLARE(pxa_clks, "marvell,pxa-clocks", pxa_dt_clocks_init);
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107
drivers/clk/pxa/clk-pxa.h
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107
drivers/clk/pxa/clk-pxa.h
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@ -0,0 +1,107 @@
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/*
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* Marvell PXA family clocks
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*
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* Copyright (C) 2014 Robert Jarzmik
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*
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* Common clock code for PXA clocks ("CKEN" type clocks + DT)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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*/
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#ifndef _CLK_PXA_
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#define _CLK_PXA_
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#define PARENTS(name) \
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static const char *name ## _parents[] __initconst
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#define MUX_RO_RATE_RO_OPS(name, clk_name) \
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static struct clk_hw name ## _mux_hw; \
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static struct clk_hw name ## _rate_hw; \
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static struct clk_ops name ## _mux_ops = { \
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.get_parent = name ## _get_parent, \
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.set_parent = dummy_clk_set_parent, \
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}; \
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static struct clk_ops name ## _rate_ops = { \
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.recalc_rate = name ## _get_rate, \
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}; \
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static struct clk *clk_register_ ## name(void) \
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{ \
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return clk_register_composite(NULL, clk_name, \
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name ## _parents, \
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ARRAY_SIZE(name ## _parents), \
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&name ## _mux_hw, &name ## _mux_ops, \
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&name ## _rate_hw, &name ## _rate_ops, \
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NULL, NULL, CLK_GET_RATE_NOCACHE); \
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}
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#define RATE_RO_OPS(name, clk_name) \
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static struct clk_hw name ## _rate_hw; \
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static struct clk_ops name ## _rate_ops = { \
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.recalc_rate = name ## _get_rate, \
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}; \
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static struct clk *clk_register_ ## name(void) \
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{ \
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return clk_register_composite(NULL, clk_name, \
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name ## _parents, \
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ARRAY_SIZE(name ## _parents), \
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NULL, NULL, \
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&name ## _rate_hw, &name ## _rate_ops, \
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NULL, NULL, CLK_GET_RATE_NOCACHE); \
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}
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/*
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* CKEN clock type
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* This clock takes it source from 2 possible parents :
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* - a low power parent
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* - a normal parent
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*
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* +------------+ +-----------+
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* | Low Power | --- | x mult_lp |
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* | Clock | | / div_lp |\
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* +------------+ +-----------+ \+-----+ +-----------+
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* | Mux |---| CKEN gate |
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* +------------+ +-----------+ /+-----+ +-----------+
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* | High Power | | x mult_hp |/
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* | Clock | --- | / div_hp |
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* +------------+ +-----------+
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*/
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struct pxa_clk_cken {
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struct clk_hw hw;
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int ckid;
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const char *name;
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const char *dev_id;
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const char *con_id;
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const char **parent_names;
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struct clk_fixed_factor lp;
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struct clk_fixed_factor hp;
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struct clk_gate gate;
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bool (*is_in_low_power)(void);
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const unsigned long flags;
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};
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#define PXA_CKEN(_dev_id, _con_id, _name, parents, _mult_lp, _div_lp, \
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_mult_hp, _div_hp, is_lp, _cken_reg, _cken_bit, flag) \
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{ .ckid = CLK_ ## _name, .name = #_name, \
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.dev_id = _dev_id, .con_id = _con_id, .parent_names = parents,\
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.lp = { .mult = _mult_lp, .div = _div_lp }, \
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.hp = { .mult = _mult_hp, .div = _div_hp }, \
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.is_in_low_power = is_lp, \
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.gate = { .reg = (void __iomem *)_cken_reg, .bit_idx = _cken_bit }, \
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.flags = flag, \
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}
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#define PXA_CKEN_1RATE(dev_id, con_id, name, parents, cken_reg, \
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cken_bit, flag) \
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PXA_CKEN(dev_id, con_id, name, parents, 1, 1, 1, 1, \
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NULL, cken_reg, cken_bit, flag)
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static int dummy_clk_set_parent(struct clk_hw *hw, u8 index)
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{
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return 0;
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}
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extern void clkdev_pxa_register(int ckid, const char *con_id,
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const char *dev_id, struct clk *clk);
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extern int clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks);
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#endif
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77
include/dt-bindings/clock/pxa-clock.h
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77
include/dt-bindings/clock/pxa-clock.h
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@ -0,0 +1,77 @@
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/*
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* Inspired by original work from pxa2xx-regs.h by Nicolas Pitre
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* Copyright (C) 2014 Robert Jarzmik
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__
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#define __DT_BINDINGS_CLOCK_PXA2XX_H__
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#define CLK_NONE 0
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#define CLK_1WIRE 1
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#define CLK_AC97 2
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#define CLK_AC97CONF 3
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#define CLK_ASSP 4
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#define CLK_BOOT 5
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#define CLK_BTUART 6
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#define CLK_CAMERA 7
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#define CLK_CIR 8
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#define CLK_CORE 9
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#define CLK_DMC 10
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#define CLK_FFUART 11
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#define CLK_FICP 12
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#define CLK_GPIO 13
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#define CLK_HSIO2 14
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#define CLK_HWUART 15
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#define CLK_I2C 16
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#define CLK_I2S 17
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#define CLK_IM 18
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#define CLK_INC 19
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#define CLK_ISC 20
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#define CLK_KEYPAD 21
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#define CLK_LCD 22
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#define CLK_MEMC 23
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#define CLK_MEMSTK 24
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#define CLK_MINI_IM 25
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#define CLK_MINI_LCD 26
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#define CLK_MMC 27
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#define CLK_MMC1 28
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#define CLK_MMC2 29
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#define CLK_MMC3 30
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#define CLK_MSL 31
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#define CLK_MSL0 32
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#define CLK_MVED 33
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#define CLK_NAND 34
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#define CLK_NSSP 35
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#define CLK_OSTIMER 36
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#define CLK_PWM0 37
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#define CLK_PWM1 38
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#define CLK_PWM2 39
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#define CLK_PWM3 40
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#define CLK_PWRI2C 41
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#define CLK_PXA300_GCU 42
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#define CLK_PXA320_GCU 43
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#define CLK_SMC 44
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#define CLK_SSP 45
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#define CLK_SSP1 46
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#define CLK_SSP2 47
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#define CLK_SSP3 48
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#define CLK_SSP4 49
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#define CLK_STUART 50
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#define CLK_TOUCH 51
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#define CLK_TPM 52
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#define CLK_UDC 53
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#define CLK_USB 54
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#define CLK_USB2 55
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#define CLK_USBH 56
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#define CLK_USBHOST 57
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#define CLK_USIM 58
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#define CLK_USIM1 59
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#define CLK_USMI0 60
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#define CLK_MAX 61
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#endif
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