32aa77a4fc
This changes the numbering scheme slightly. Previously the ordering was coming out like this: Rx-2 Rx-1 Rx-0 TxRx-0 Which would drop two queues on CPU 0. This change makes it so that the ordering is like this: Rx-3 Rx-2 Rx-1 TxRx-0 This means that each CPU will have it's own Rx queue, and only CPU 0 will have the Tx queue. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> |
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| .. | ||
| ixgbe.h | ||
| ixgbe_82598.c | ||
| ixgbe_82599.c | ||
| ixgbe_common.c | ||
| ixgbe_common.h | ||
| ixgbe_dcb.c | ||
| ixgbe_dcb.h | ||
| ixgbe_dcb_82598.c | ||
| ixgbe_dcb_82598.h | ||
| ixgbe_dcb_82599.c | ||
| ixgbe_dcb_82599.h | ||
| ixgbe_dcb_nl.c | ||
| ixgbe_ethtool.c | ||
| ixgbe_fcoe.c | ||
| ixgbe_fcoe.h | ||
| ixgbe_main.c | ||
| ixgbe_mbx.c | ||
| ixgbe_mbx.h | ||
| ixgbe_phy.c | ||
| ixgbe_phy.h | ||
| ixgbe_sriov.c | ||
| ixgbe_sriov.h | ||
| ixgbe_type.h | ||
| Makefile | ||