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ixgbe: change vector numbering so that queues end up on correct CPUs

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This changes the numbering scheme slightly. Previously the ordering was
coming out like this:
Rx-2
Rx-1
Rx-0
TxRx-0
Which would drop two queues on CPU 0. This change makes it so that the
ordering is like this:
Rx-3
Rx-2
Rx-1
TxRx-0
This means that each CPU will have it's own Rx queue, and only CPU 0 will
have the Tx queue.

Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Alexander Duyck 2010-11-16 19:26:59 -08:00 committed by Jeff Kirsher
parent b953799ee2
commit 32aa77a4fc
1 changed files with 4 additions and 2 deletions
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6
drivers/net/ixgbe/ixgbe_main.c
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@ -2182,9 +2182,11 @@ static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
} else if (handler == &ixgbe_msix_clean_tx) {
sprintf(adapter->name[vector], "%s-%s-%d",
netdev->name, "tx", ti++);
} else
} else {
sprintf(adapter->name[vector], "%s-%s-%d",
netdev->name, "TxRx", vector);
netdev->name, "TxRx", ri++);
ti++;
}
err = request_irq(adapter->msix_entries[vector].vector,
handler, 0, adapter->name[vector],