Else on SMP systems it is possible for hotplug to execute,
invoke tg3_open(), and end up loading the uninitialized
PCI register save area into the card.
Signed-off-by: David S. Miller <davem@davemloft.net>
Add 5780S support by adding a new tg3_setup_fiber_mii_phy() function and
a timer function for parallel link detection. 5780S uses standard MII
registers for 1000BaseX and runs in GMII mode as opposed to TBI mode on
older serdes chips.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Disallow jumbo TSO on 5780 due to hardware restrictions.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Consolidate all DMA watermark settings for standard and jumbo frames on
all chips in tg3_init_bufmgr_config() and add new settings for 5780.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add a new rx_pkt_buf_sz to the tg3 structure to support variable buffer
sizes on the standard ring.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add basic jumbo frames support for 5780. This chip supports jumbo frames
on the standard receive ring without the jumbo ring. The
TG3_FLAG_JUMBO_ENABLE is changed to TG3_FLAG_JUMBO_RING_ENABLE to
indicate using the jumbo ring on 5704 and older chips. A new
TG3_FLG2_JUMBO_CAPABLE flag is added to indicate jumbo frames support
with or without the jumbo ring.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add 5780 PCI IDs, chip IDs, and other basic support.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add support for ethtool -C with verification of user parameters.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
1. Move tp->irq_sync = 0 to before the interrupt mailbox IO in
tg3_enable_ints() so that the interrupt handler will always see
irq_sync == 0 when interrupts are enabled.
2. Remove the tg3_enable_ints() call in tg3_reset_hw(). Interrupts are
always enabled explicitly or through tg3_netif_start(). This is to
prevent interrupts being enabled while poll is disabled.
3. Update trans_start with jiffies in tg3_netif_stop() to prevent false
NETDEV WATCHDOG.
4. Pass in the proper irq_sync parameter to tg3_full_lock() depending on
netif_running() in some of the ethtool set calls.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Move all driver spinlocks to be taken at sw IRQ
context only.
This fixes the skb_copy() we were doing with hw
IRQs disabled (which is illegal and triggers a
BUG() with HIGHMEM enabled). It also simplifies
the locking all over the driver tremendously.
We accomplish this feat by creating a special
sequence to synchronize with the hw IRQ handler
using a binary state and synchronize_irq().
This idea is from Herbert Xu.
Thanks to Michael Chan for helping to track down
all of the race conditions in initial versions
of this code.
Signed-off-by: David S. Miller <davem@davemloft.net>
There must be a rmb() between reading the status block tag
and calling tg3_has_work(). This was missing in tg3_mis()
and tg3_interrupt_tagged(). tg3_poll() got it right.
Also, SD_STATUS_UPDATED must be cleared in the status block
right before we call tg3_has_work(). Only tg3_poll() got this
wrong.
Based upon patches and commentary from Grant Grundler and
Michael Chan.
Signed-off-by: David S. Miller <davem@davemloft.net>
Fix 5700/5701 DMA write corruption on Apple G4 by detecting the Apple
UniNorth PCI 1.5 chipset and adjusting the DMA write boundary to 16. DMA
test fails to detect the problem with this chipset.
Thanks to Manuel Perez Ayala for reporting the problem and helping to
debug it.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
On some 5701 devices with older bootcode, the LED configuration bits in
SRAM may be invalid with value zero. The fix is to check for invalid
bits (0) and default to PHY 1 mode. Incorrect LED mode will lead to
error in programming the PHY.
Thanks to Grant Grundler for debugging the problem.
>From Grant:
| In May, 2004, tg3 v3.4 changed how MAC_LED_CTRL (0x40c) was getting
| programmed and how to determine what to program into LED_CTRL. The new
| code trusted NIC_SRAM_DATA_CFG (0x00000b58) to indicate what to write
| to LED_CTRL and MII EXT_CTRL registers. On "IOX Core Lan", SRAM was
| saying MODE_MAC (0x0) and that doesn't work.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add tg3_nvram_lock() and tg3_nvram_unlock() calls around tg3_halt_cpu().
It is possible that the bootcode may be loading code from nvram during
this call and stopping the cpu without getting the lock may cause
uncompleted nvram data to be left in the nvram data register. Subsequent
calls to read/write nvram data will fail.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This test uses the previously added tg3_test_interrupt() to perform the
test.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The test will loopback one packet in MAC loopback mode and verify the
packet data.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add a reset kind parameter to tg3_halt() so that the RESET_KIND_SUSPEND
parameter can be passed to tg3_halt() before doing offline tests.
All other calls to tg3_halt() will use the RESET_KIND_SHUTDOWN
parameter.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add 0x1601 as 5752M, it's a 5752 but for mobile PCs.
Stolen from Broadcom bcm5700-8.1.55 driver.
Someone forgot to add it to tg3 ;-)
Signed-off-by: David S. Miller <davem@davemloft.net>
Extract DMA boundary bit selection into a seperate
function, tg3_calc_dma_bndry(). Call this from
tg3_test_dma().
Make DMA test more reliable by using no DMA boundry
setting during the test. If the test passes, then
use the setting we selected before the test.
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Even though we do software interrupt mitigation
via NAPI, it still helps to have some minimal
hw assisted mitigation.
This helps, particularly, on systems where register
I/O overhead is much greater than the CPU horsepower.
For example, it helps on NUMA systems. In such cases
the PIO overhead to disable interrupts for NAPI accounts
for the majority of the packet processing cost. The
CPU is fast enough such that only a single packet is
processed by each NAPI poll call.
Thanks to Michael Chan for reviewing this patch.
Signed-off-by: David S. Miller <davem@davemloft.net>
When supported, use the TAGGED interrupt processing support
the chip provides. In this mode, instead of a "on/off" binary
semaphore, an incrementing tag scheme is used to ACK interrupts.
All MSI supporting chips support TAGGED mode, so the tg3_msi()
interrupt handler uses it unconditionally. This invariant is
verified when MSI support is tested.
Since we can invoke tg3_poll() multiple times per interrupt under
high packet load, we fetch a new copy of the tag value in the
status block right before we actually do the work.
Also, because the tagged status tells the chip exactly which
work we have processed, we can make two optimizations:
1) tg3_restart_ints() need not check tg3_has_work()
2) the tg3_timer() need not poke the chip 10 times per
second to keep from losing interrupt events
Based upon valuable feedback from Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
tg3_stop_block() errors can be safely ignored since tg3_chip_reset()
always follows tg3_stop_block() calls.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
tg3_restart_ints() is called to re-enable interrupts after tg3_poll()
has finished all the work. It calls tg3_cond_int() to force an interrupt
if the status block updated bit is set. The updated bit will be set if
there is a new status block update sometime during tg3_poll() and it can
be very often. The worst part is that even if all the work has been
processed, the updated bit remains set and an interrupt will be forced
unnecessarily.
The fix is to call tg3_has_work() instead to determine if new work is
posted before forcing an interrupt. The way to force an interrupt is
also changed to use "coalesce_now" instead of "SETINT". The former is
generally a safer way to force the interrupt.
Also deleted the first parameter to tg3_has_work() which is unused.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch refreshes the hw rx producer in tg3_rx() so that additional
work posted by the hardware can be processed.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch fixes a bug that causes tg3_has_work() to always return 1.
rx work is determined by comparing tp->rx_rcb_ptr with the current hw
producer index. The hw producer index is modulo the ring size, but tp-
>rx_rcb_ptr is a free running counter that goes up beyond the ring size.
After the ring wraps around once, tg3_has_work() will always return 1.
The fix is to always do modulo arithmetic on tp->rx_rcb_ptr.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add MSI test for chips that support MSI. If MSI test fails, it will
switch back to INTx mode and will print a message asking the user to
report the failure.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Fix a bug in tg3_set_eeprom() when the length is less than 4 and the
offset is not 4-byte aligned.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add support for the NVRAM lock-out feature for TPM in 5752. If lock-out
is enabled, certain NVRAM registers cannot be written to.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add bit definitions for the new GPIO3 in 5752. GPIO3 must be driven as
output when it is unused.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
