i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Implementation of USB device driver integrated in Freescale's i.MXL
processor.
Adds USB device driver for i.MXL.
Signed-off-by: Darius Augulis <augulis.darius@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This patch removes the inclusion of mach/hardware.h from mach/irqs.h and
switches to more meaningful names for the irq related macros.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Drivers which are going to use it will have to select it and use
mxc_set_irq_fiq() to set FIQ mode for this interrupt.
Signed-off-by: Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Adds MX1 architecture to platform MXC. It will supersede mach-imx
and let it die.
Signed-off-by: Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
Signed-off-by: Darius Augulis <augulis.darius@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fix GIUS register setup in the mxc_gpio_mode().
Signed-off-by: Darius Augulis <augulis.darius@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
pins definition for UART5 when used in alternate mode 2
Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
UART2 pins when used in functionnal mode
Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add basic support to the MX31PDK development board, also known
as MX31 3DS or MX31 3-stack board (http://www.freescale.com/imx31pdk).
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: sascha Hauer <s.hauer@pengutronix.de>
mxc_gpio_setup_multiple_pins used to take several ALLOC_MODE flags. Most
of them are unused, so simplify the function by removing the flags. Also,
instead of using a confusing MXC_GPIO_ALLOC_MODE_RELEASE flag in a function
having alloc in its name, add a mxc_gpio_release_multiple_pins function.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The EMMA (Enhanced Multimedia Engine) is divided into two parts, the
postprocessor and the preprocessor. Fix the base addresses.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This one updates DMA support on MX2 which got broken in:
[ARM] Hide ISA DMA API when ISA_DMA_API is unset
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As Al did for Versatile in 2ad4f86b60,
add a typesafe __io implementation for platforms to use. Convert
platforms to use this new simple typesafe implementation.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When ISA_DMA_API is unset, we're not implementing the ISA DMA API,
so there's no point in publishing the prototypes via asm/dma.h, nor
including the machine dependent parts of that API.
This allows us to remove a lot of mach/dma.h files which don't contain
any useful code. Unfortunately though, some platforms put their own
private non-ISA definitions into mach/dma.h, so we leave these behind
and fix the appropriate #include statments.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Let's provide an overridable default instead of having every machine
class define __virt_to_bus and __bus_to_virt to the same thing. What
most platforms are using is bus_addr == phys_addr so such is the default.
One exception is ebsa110 which has no DMA what so ever, so the actual
definition is not important except only for proper compilation. Also
added a comment about the special footbridge bus translation.
Let's also remove comments alluding to set_dma_addr which is not
(and should not) be commonly used.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The internal devices of the MX3 Processor have to be mapped
MT_DEVICE_NONSHARED devices, otherwise cache corruptions occur.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* git://git.infradead.org/mtd-2.6: (69 commits)
Revert "[MTD] m25p80.c code cleanup"
[MTD] [NAND] GPIO driver depends on ARM... for now.
[MTD] [NAND] sh_flctl: fix compile error
[MTD] [NOR] AT49BV6416 has swapped erase regions
[MTD] [NAND] GPIO NAND flash driver
[MTD] cmdlineparts documentation change - explain where mtd-id comes from
[MTD] cfi_cmdset_0002.c: Add Macronix CFI V1.0 TopBottom detection
[MTD] [NAND] Fix compilation warnings in drivers/mtd/nand/cs553x_nand.c
[JFFS2] Write buffer offset adjustment for NOR-ECC (Sibley) flash
[MTD] mtdoops: Fix a bug where block may not be erased
[MTD] mtdoops: Add a magic number to logged kernel oops
[MTD] mtdoops: Fix an off by one error
[JFFS2] Correct parameter names of jffs2_compress() in comments
[MTD] [NAND] sh_flctl: add support for Renesas SuperH FLCTL
[MTD] [NAND] Bug on atmel_nand HW ECC : OOB info not correctly written
[MTD] [MAPS] Remove unused variable after ROM API cleanup.
[MTD] m25p80.c extended jedec support (v2)
[MTD] remove unused mtd parameter in of_mtd_parse_partitions()
[MTD] [NAND] remove dead Kconfig associated with !CONFIG_PPC_MERGE
[MTD] [NAND] driver extension to support NAND on TQM85xx modules
...
This patch adds DMA support for Freescale i.MX27 SoCs. It is derived
from the i.MX1 port and should (though currently untested) still be
working for the i.MX1.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fix some base address declaration by adding a cast.
Signed-off-by: Luotao Fu <l.fu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This one adds definitions to configure RTCK pad (PE16) in primary and alternate
function. The RTCK Pin is used by one wire master controller and as JTAG Clock
return.
Signed-off-by: Luotao Fu <l.fu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds macros to get CSCR upper, lower and additional registers.
These registers are needed to configure a chip select line. The offset
layouts of these Registers are identical on mx27 and mx31, hence we can
use the macros in generic way
Signed-off-by: Luotao Fu <l.fu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
this adds convenience values usable by mxc_iomux_mode() to configure Pins of the
spi interfaces on mx31.
Signed-off-by: Luotao Fu <l.fu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Needed for 8250 serial port and CS89x0 ethernet interface.
Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch adds support for the integrated NAND flash controller of the
i.MX2 and i.MX3 family. It is tested on MX27 but should work on MX3
aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Juergen Beisert <j.beisert@pengutronix.de>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
