This patch adds GPIOlib support for S5PV210.
Signed-off-by: Pannaga Bhushan <p.bhushan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Timer interrupts range was defined as 43-47, what overlaps with VIC0 range
(32-64). This was caused probably by a typo while the common interrupts
definition was refactored. This patch moves timer interrupt range to safe
area of 11-15 (just before uart range).
This fixes the commit 87aef30eb3
("ARM: S5P: Change S5P_TIMER_IRQ based to 11 for SAMSUNG S5P series.")
which meant to move these into the old (and previously reserved)
ISA space.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[ben-linux@fluff.org: update description]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
The pm-gpio.c code was incrementing the gpio_nr from the nr_gpios
field and the bank-bank offset inside the loop, and also in the
for() loop with a ++.
Remove the ++, as the number is already at the next GPIO, thus
ensuring that we don't skip a gpio bank by accident.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
As part of the cleanup, remove the old macros mapping GPIO numbers
to the base of the register now we have gpiolib to manage the GPIO
mappings for us.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Update a couple of S3C24XX and S3C2412 files that are still
using the GPIO number to register mapping calls to get the
s3c_gpio_chip and use the base field from that.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Start cleaning up the numbering of GPIO banks by removing the old
bank start definitions currently being used by some of the header
files.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Increase GPIOs number for S3C244X, and make S3C_GPIO_END
point to BANKJ end, otherwise gpiolib refuses to register
BANKJ
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[ben-linux@fluff.org: Move pm fix to new patch]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Move the S3C_FB_MAX_WIN to the platform data to avoid
having to include the registers with the platform data.
Set S3C_FB_MAX_WIN to 5, which is the maximum that any
of the current hardware can do and the cost of having
it set to this for all is minimal (at least for the
platform data case), then always leave this as the maximum
for the systems supported.
Also remove the inclusion of <mach/regs-fb.h> from
the device definition in arch/arm/plat-samsung
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Fix the definition of the LCD clock bit, it is the TFT display
controller on bit 9, not the older STN on bit 10.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This adds the xusbxti clock to S3C64XX platform.
Signed-off-by: Maurus Cuelenaere <mcuelenaere@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Seems like a typo, wrong setup leads to broken image on ipaq screen.
Signed-off-by: Mike Solovyev <ms@sk.2-ch.org>
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
All other functions have the channel argument of type 'unsigned int'
the s3c2410_dma_devconfig also accept the same value as argument but
treat it as type 'int'. Remove this anomaly by make it 'unsigned int'.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Add sclk clocks of type 'struct clksrc_clk' clock. The 'group2' of
clock clock sources is also added. This patch also changes the the
'id' member value of the uclk1 clock for instance instance 0 since
there are 4 instances of the uclk1 clock.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Add the sclk_audio(0/1/2) clocks and sclk_spdif clock of type
'struct clksrc_clk' clock. Also, add clk_pcmcdclk(0/1/2) clocks
of type 'struct clk' clock.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Add sclk_dac, sclk_mixer and sclk_hdmi clocks. These clocks
are of type 'struct clksrc_clk' and so have a corresponding
clock list. These clocks are also added to the list of
clocks to be registered at boot time.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This patch adds the following system clocks.
1. clk_sclk_hdmiphy
2. clk_sclk_usbphy0
3. clk_sclk_usbphy1
4. sclk_dmc (dram memory controller clock)
5. sclk_onenand
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This patch adds the following.
1. Adds 'clk_sclk_hdmi27m' clock to represent the HDMI 27MHz clock.
2. Adds 'clk_vpllsrc; clock of type clksrc_clk to represent the
input clock for VPLL.
3. Adds 'clk_sclk_vpll' clock of type clksrc_clk to represent the
output of the MUX_VPLL mux.
4. Add clk_sclk_hdmi27m, clk_vpllsrc and clk_sclk_vpll to the list
of clocks to be registered.
5. Adds boot time print of 'clk_sclk_vpll' clock rate.
6. Adds 'clk_fout_vpll' clock to plat-s5p such that it is reusable
on other s5p platforms.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
The clk_p83 clock, which is the PCLK clock for PSYS domain, is of
type 'struct clk' whereas on S5PV210, this clock is suitable to be
of type clksrc_clk clock (since it has a clock divider). So this
patch replaces the 'struct clk' type clock to 'struct clksrc_clk'
type clock for the PCLK PSYS clock.
This patch modifies the following.
1. Removes definitions and usage of 'clk_p66' clock.
2. Adds 'clk_pclk_psys' clock which is of type 'struct clksrc_clk'.
3. Replaces all usage of clk_p66 with clk_pclk_psys clock.
4. Adds clk_pclk_psys into list of clocks to be registered.
5. Removes the sys_clks array since it is no longer required.
Also the registration of clocks in sys_clks is also removed.
6. Remove the 'GET_DIV' as it is no longer required.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
The clk_p83 clock, which is the PCLK clock for DSYS domain, is of
type 'struct clk' whereas on S5PV210, this clock is suitable to be
of type clksrc_clk clock (since it has a clock divider). So this
patch replaces the 'struct clk' type clock to 'struct clksrc_clk'
type clock for the PCLK DSYS clock.
This patch modifies the following.
1. Remove definitions and usage of 'clk_p83' clock.
2. Adds 'clk_pclk_dsys' clock which is of type 'struct clksrc_clk'.
3. Replace all usage of clk_p83 with clk_pclk_dsys clock.
4. Adds clk_pclk_dsys into list of clocks to be registered.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
The clk_h100 clock represents the IMEM clock for the MSYS domain.
This clock rate of this clock is always half of the hclk_msys clock.
There is an issue when getting the clock rate of the clk_h100 clock
(clock get_rate hclk_h100 always returns clock rate that is equal to
the hclk_msys clock rate).
This patch modifies the following.
1. Moves the definition of the clk_h100 clock into the 'init_clocks'
list with the appropriate parent, ctrlbit, enable and ops fields.
2. The name of the clock is changed from 'clk_h100' to 'hclk_imem'
to represent more clearly that is represents the IMEM clock in
the MSYS domain.
3. The function to get the clock rate of the hclk_imem clock is added.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
The clk_p100 clock, which is the PCLK clock for MSYS domain, is of
type 'struct clk' whereas on S5PV210, this clock is suitable to be
of type clksrc_clk clock (since it has a choice of clock source
and a pre-divider). So this patch replaces the 'struct clk' type
clock to 'struct clksrc_clk' type clock for the PCLK MSYS clock.
This patch modifies the following.
1. Remove definitions and usage of 'clk_p100' clock.
2. Adds 'clk_pclk_msys' clock which is of type 'struct clksrc_clk'.
3. Replace all usage of clk_p100 with clk_pclk_msys clock.
4. Adds clk_pclk_msys into list of clocks to be registered.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
The clk_h133 clock, which is the HCLK clock for PSYS domain, is of
type 'struct clk' whereas on S5PV210, this clock is suitable to be
of type clksrc_clk clock (since it has a choice of clock source
and a pre-divider). So this patch replaces the 'struct clk' type
clock to 'struct clksrc_clk' type clock for the HCLK PSYS clock.
This patch modifies the following.
1. Remove definitions and usage of 'clk_h133' clock.
2. Adds 'clk_hclk_psys' clock which is of type 'struct clksrc_clk'.
3. Replace all usage of clk_h133 with clk_hclk_psys clock.
4. Adds clk_hclk_psys into list of clocks to be registered.
5. Removes the clock rate calculation of hclk133 and replaces
it with code that derives the HCLK PSYS clock rate from
the clk_hclk_psys clock.
6. Modify printing of the system clock rates.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
The clk_h166 clock, which is the HCLK clock for DSYS domain, is of
type 'struct clk' whereas on S5PV210, this clock is suitable to be
of type clksrc_clk clock (since it has a choice of clock source
and a pre-divider). So this patch replaces the 'struct clk' type
clock to 'struct clksrc_clk' type clock for the HCLK DSYS clock.
This patch modifies the following.
1. Remove definitions and usage of 'clk_h166' clock.
2. Adds 'clk_sclk_a2m' clock which is one of possible parent clock
sources for the DSYS HCLK clock.
3. Adds 'clk_hclk_dsys' clock which is of type 'struct clksrc_clk'.
4. Replace all usage of clk_h166 with clk_hclk_dsys clock.
5. Adds clk_sclk_a2m and clk_hclk_dsys into list of clocks to
be registered.
6. Removes the clock rate calculation of hclk166 and replaces
it with code that derives the HCLK DSYS clock rate from
the clk_hclk_dsys clock.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
The clk_h200 represents the HCLK for the MSYS domain. This clock
is of type 'struct clk' but on V210, it is more suitable to be of
type 'struct clksrc_clk' (since it is a divided version of the
armclk). The replacement clock is renamed as clk_hclk_msys to
indicate that it represents the HCLK for MSYS domain.
This patch modifies the following.
1. Removes the usage of the clk_h200 clock.
2. Adds the new clock 'clk_hclk_msys'.
3. Adds clk_hclk_msys to the list of sysclks to be registered.
4. Modifies the hclk_msys clock rate calculation procedure to
be based on the new clk_hclk_msys clock.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This patch modifies the following.
1. Adds arm clock 'clk_armclk' of type clksrc_clk clock type.
2. Adds arm clock to the list of system clocks 'sysclks' for
registering it along with other system clocks.
3. Modifies the armclk clock rate calculation procedure to be
based on the new clk_armclk clock.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
The assignment of clock rates for fout apll/mpll/epll is moved further
up in the s5pv210_setup_clocks function because the subsequent patches
require the clock rate of fout clocks to be setup.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This patch modifies the following.
1. Registers the mout_apll clksrc_clk clock.
2. The mout_mpll and mout_epll clocks were registered as 'struct clk'
types and then their parents were setup using the s3c_set_clksrc
function. This patch reduces the two steps into one by registering
the mout_mpll and mout_epll clocks using the s3c_register_clksrc
function.
3. As per point 2 above, the init_parents array is no longer required.
So the mout clocks are now put together in a new array named 'sysclks'.
The sysclks array will list the system level clocks and more
clocks will be added to it in the subsequent patches.
4. The clks array is left empty because of the movement of mpll and epll
clocks into the sysclks array. It is not deleted since subsequent
patches will add clocks into this array.
Signed-off-by: Thomas Abraham <thomas.ab <at> samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim <at> samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
The system clock definitions are currently defined below the
peripheral clock definitions in the V210 clock code. For the V210
clock updates that follow this patch, it is required that the
system clock definitions such as the mout_apll and mout_mpll be
defined prior to the device clock definitions. This patch
re-arranges the system clock defintions for the clock updates that
follow this patch.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Declare 'audio-bus' clock for IISv4 controller of S3C6410.
Even though the name is same as that for IISv3, the id is
set to -1(just one instance of the controller is available)
which helps always fetch the correct clock.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Declare possible sources of CLKAUDIO[2]/audio-bus for IISv4 controller.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Declare the source of clock provided at Xi2sCDCLK2 pin for IISv4 controller.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This patch adds the following.
1. Add new definitions of clock of type 'struct clksrc_clk'.
2. Add gate control function for GATE_SCLK1 which is required
for new clock additions.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
The clock source options avaialable in the clkset_mmc_spi are
applicable to clocks such as sclk_post, sclk_dispcon and
sclk_fimgvg. So this set is renamed as clkset_group1 to indicate
that it can be used as clock sources for other clocks and not
just for sclk_spi and sclk_mmc clocks.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Add definitions of clocks of type 'struct clk'.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
