ARM: S5PV210: Register apll/mpll/epll clksrc_clk clocks
This patch modifies the following. 1. Registers the mout_apll clksrc_clk clock. 2. The mout_mpll and mout_epll clocks were registered as 'struct clk' types and then their parents were setup using the s3c_set_clksrc function. This patch reduces the two steps into one by registering the mout_mpll and mout_epll clocks using the s3c_register_clksrc function. 3. As per point 2 above, the init_parents array is no longer required. So the mout clocks are now put together in a new array named 'sysclks'. The sysclks array will list the system level clocks and more clocks will be added to it in the subsequent patches. 4. The clks array is left empty because of the movement of mpll and epll clocks into the sysclks array. It is not deleted since subsequent patches will add clocks into this array. Signed-off-by: Thomas Abraham <thomas.ab <at> samsung.com> Signed-off-by: Kukjin Kim <kgene.kim <at> samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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1 changed files with 4 additions and 6 deletions
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@ -324,7 +324,7 @@ static struct clksrc_clk clksrcs[] = {
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};
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/* Clock initialisation code */
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static struct clksrc_clk *init_parents[] = {
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static struct clksrc_clk *sysclks[] = {
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&clk_mout_apll,
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&clk_mout_epll,
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&clk_mout_mpll,
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@ -411,16 +411,11 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
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clk_h166.rate = hclk166;
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clk_h200.rate = hclk200;
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for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
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s3c_set_clksrc(init_parents[ptr], true);
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for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
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s3c_set_clksrc(&clksrcs[ptr], true);
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}
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static struct clk *clks[] __initdata = {
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&clk_mout_epll.clk,
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&clk_mout_mpll.clk,
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};
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void __init s5pv210_register_clocks(void)
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@ -433,6 +428,9 @@ void __init s5pv210_register_clocks(void)
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if (ret > 0)
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printk(KERN_ERR "Failed to register %u clocks\n", ret);
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for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
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s3c_register_clksrc(sysclks[ptr], 1);
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s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
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s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
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