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mfd: db8500-prcmu: Update stored DSI PLL divider value

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Previously the DSI PLL divider rate was initialised statically and
assumed to be 1. Before the common clock framework was enabled for
ux500, a call to clk_set_rate() would always update the HW registers
no matter what the current setting was.

This patch makes sure the actual hw settings and the sw assumed
settings are matched.

Signed-off-by: Paer-Olof Haakansson <par-olof.hakansson@stericsson.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Ulf Hansson 2013-05-14 15:14:55 +02:00 committed by Samuel Ortiz
parent 0b8ebdb188
commit e9d7b4b569
1 changed files with 2 additions and 0 deletions
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2
drivers/mfd/db8500-prcmu.c
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@ -1613,6 +1613,8 @@ static unsigned long dsiclk_rate(u8 n)
if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
divsel = dsiclk[n].divsel;
else
dsiclk[n].divsel = divsel;
switch (divsel) {
case PRCM_DSI_PLLOUT_SEL_PHI_4: