From e9d7b4b5691cac4dce6c5eed9e217e50e24edef7 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 14 May 2013 15:14:55 +0200 Subject: [PATCH] mfd: db8500-prcmu: Update stored DSI PLL divider value Previously the DSI PLL divider rate was initialised statically and assumed to be 1. Before the common clock framework was enabled for ux500, a call to clk_set_rate() would always update the HW registers no matter what the current setting was. This patch makes sure the actual hw settings and the sw assumed settings are matched. Signed-off-by: Paer-Olof Haakansson Signed-off-by: Ulf Hansson signed-off-by: Lee Jones Signed-off-by: Samuel Ortiz --- drivers/mfd/db8500-prcmu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 5389368e0e5f..66f80973596b 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -1613,6 +1613,8 @@ static unsigned long dsiclk_rate(u8 n) if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) divsel = dsiclk[n].divsel; + else + dsiclk[n].divsel = divsel; switch (divsel) { case PRCM_DSI_PLLOUT_SEL_PHI_4: