drm/i915: set phase sync pointer override enable before setting phase sync pointer
We need to unlock the phase sync pointer enable bit before we can actually enable the phase sync pointer workaround on Ironlake. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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0fc932b8ec
commit
6f06ce184c
2 changed files with 11 additions and 4 deletions
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@ -3005,7 +3005,8 @@
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#define FDI_RXA_CHICKEN 0xc200c
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#define FDI_RXB_CHICKEN 0xc2010
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#define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
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#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
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#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
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#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN)
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#define SOUTH_DSPCLK_GATE_D 0xc2020
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@ -2273,7 +2273,11 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
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udelay(150);
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/* Ironlake workaround, enable clock pointer after FDI enable*/
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I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
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if (HAS_PCH_IBX(dev)) {
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I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
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I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
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FDI_RX_PHASE_SYNC_POINTER_EN);
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}
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reg = FDI_RX_IIR(pipe);
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for (tries = 0; tries < 5; tries++) {
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@ -2516,10 +2520,12 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
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udelay(100);
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/* Ironlake workaround, disable clock pointer after downing FDI */
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if (HAS_PCH_IBX(dev))
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if (HAS_PCH_IBX(dev)) {
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I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
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I915_WRITE(FDI_RX_CHICKEN(pipe),
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I915_READ(FDI_RX_CHICKEN(pipe) &
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~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
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~FDI_RX_PHASE_SYNC_POINTER_EN));
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}
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/* still set train pattern 1 */
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reg = FDI_TX_CTL(pipe);
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