drm/i915: factor out FDI disable and add FDI assertions
Factor out the FDI disable function (make it a mirror of ironlake_fdi_enable) and add some FDI related assertions to the FDI training code (we need an active pipe & plane before we start transmitting bits). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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040484af3a
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0fc932b8ec
1 changed files with 60 additions and 44 deletions
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@ -2237,8 +2237,13 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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u32 reg, temp, tries;
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/* FDI needs bits from pipe & plane first */
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assert_pipe_enabled(dev_priv, pipe);
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assert_plane_enabled(dev_priv, plane);
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/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
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for train result */
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reg = FDI_RX_IMR(pipe);
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@ -2487,6 +2492,60 @@ static void ironlake_fdi_enable(struct drm_crtc *crtc)
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}
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}
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static void ironlake_fdi_disable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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u32 reg, temp;
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/* disable CPU FDI tx and PCH FDI rx */
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reg = FDI_TX_CTL(pipe);
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temp = I915_READ(reg);
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I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
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POSTING_READ(reg);
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reg = FDI_RX_CTL(pipe);
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temp = I915_READ(reg);
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temp &= ~(0x7 << 16);
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temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
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I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
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POSTING_READ(reg);
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udelay(100);
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/* Ironlake workaround, disable clock pointer after downing FDI */
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if (HAS_PCH_IBX(dev))
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I915_WRITE(FDI_RX_CHICKEN(pipe),
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I915_READ(FDI_RX_CHICKEN(pipe) &
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~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
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/* still set train pattern 1 */
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reg = FDI_TX_CTL(pipe);
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temp = I915_READ(reg);
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_PATTERN_1;
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I915_WRITE(reg, temp);
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reg = FDI_RX_CTL(pipe);
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temp = I915_READ(reg);
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if (HAS_PCH_CPT(dev)) {
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temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
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temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
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} else {
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_PATTERN_1;
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}
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/* BPC in FDI rx is consistent with that in PIPECONF */
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temp &= ~(0x07 << 16);
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temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
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I915_WRITE(reg, temp);
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POSTING_READ(reg);
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udelay(100);
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}
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/*
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* When we disable a pipe, we need to clear any pending scanline wait events
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* to avoid hanging the ring, which we assume we are waiting on.
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@ -2691,50 +2750,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
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I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
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/* disable CPU FDI tx and PCH FDI rx */
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reg = FDI_TX_CTL(pipe);
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temp = I915_READ(reg);
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I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
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POSTING_READ(reg);
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reg = FDI_RX_CTL(pipe);
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temp = I915_READ(reg);
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temp &= ~(0x7 << 16);
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temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
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I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
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POSTING_READ(reg);
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udelay(100);
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/* Ironlake workaround, disable clock pointer after downing FDI */
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if (HAS_PCH_IBX(dev))
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I915_WRITE(FDI_RX_CHICKEN(pipe),
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I915_READ(FDI_RX_CHICKEN(pipe) &
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~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
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/* still set train pattern 1 */
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reg = FDI_TX_CTL(pipe);
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temp = I915_READ(reg);
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_PATTERN_1;
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I915_WRITE(reg, temp);
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reg = FDI_RX_CTL(pipe);
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temp = I915_READ(reg);
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if (HAS_PCH_CPT(dev)) {
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temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
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temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
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} else {
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_PATTERN_1;
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}
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/* BPC in FDI rx is consistent with that in PIPECONF */
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temp &= ~(0x07 << 16);
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temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
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I915_WRITE(reg, temp);
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POSTING_READ(reg);
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udelay(100);
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ironlake_fdi_disable(crtc);
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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temp = I915_READ(PCH_LVDS);
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