2005-04-16 16:20:36 -06:00
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/*
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* AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
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* IDE driver for Linux.
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*
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* Copyright (c) 2000-2002 Vojtech Pavlik
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2010-01-18 00:18:17 -07:00
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* Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
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2005-04-16 16:20:36 -06:00
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*
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* Based on the work of:
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* Andre Hedrick
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*/
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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2008-07-24 14:53:32 -06:00
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#define DRV_NAME "amd74xx"
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2008-02-01 15:09:30 -07:00
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enum {
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AMD_IDE_CONFIG = 0x41,
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AMD_CABLE_DETECT = 0x42,
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AMD_DRIVE_TIMING = 0x48,
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AMD_8BIT_TIMING = 0x4e,
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AMD_ADDRESS_SETUP = 0x4c,
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AMD_UDMA_TIMING = 0x50,
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2005-04-16 16:20:36 -06:00
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};
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static unsigned int amd_80w;
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static unsigned int amd_clock;
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2007-07-09 15:17:57 -06:00
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static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
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2005-04-16 16:20:36 -06:00
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static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
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2008-02-01 15:09:30 -07:00
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static inline u8 amd_offset(struct pci_dev *dev)
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{
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return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0;
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}
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2005-04-16 16:20:36 -06:00
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/*
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* amd_set_speed() writes timing values to the chipset registers
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*/
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2008-02-01 15:09:30 -07:00
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static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,
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struct ide_timing *timing)
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2005-04-16 16:20:36 -06:00
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{
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2008-02-01 15:09:30 -07:00
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u8 t = 0, offset = amd_offset(dev);
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2005-04-16 16:20:36 -06:00
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2008-02-01 15:09:30 -07:00
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pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t);
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2008-07-15 13:21:41 -06:00
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t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
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2008-02-01 15:09:30 -07:00
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pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t);
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2005-04-16 16:20:36 -06:00
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2008-02-01 15:09:30 -07:00
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pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)),
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2008-07-15 13:21:41 -06:00
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((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));
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2005-04-16 16:20:36 -06:00
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2008-02-01 15:09:30 -07:00
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pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn),
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2008-07-15 13:21:41 -06:00
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((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));
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2005-04-16 16:20:36 -06:00
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2008-02-01 15:09:30 -07:00
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switch (udma_mask) {
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2008-07-15 13:21:41 -06:00
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case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
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case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break;
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case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break;
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case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break;
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2007-07-09 15:17:57 -06:00
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default: return;
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2005-04-16 16:20:36 -06:00
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}
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2010-01-18 00:18:17 -07:00
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if (timing->udma)
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pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + 3 - dn, t);
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2005-04-16 16:20:36 -06:00
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}
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/*
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ide: move ide_config_drive_speed() calls to upper layers (take 2)
* Convert {ide_hwif_t,ide_pci_device_t}->host_flag to be u16.
* Add IDE_HFLAG_POST_SET_MODE host flag to indicate the need to program
the host for the transfer mode after programming the device. Set it
in au1xxx-ide, amd74xx, cs5530, cs5535, pdc202xx_new, sc1200, pmac
and via82cxxx host drivers.
* Add IDE_HFLAG_NO_SET_MODE host flag to indicate the need to completely
skip programming of host/device for the transfer mode ("smart" hosts).
Set it in it821x host driver and check it in ide_tune_dma().
* Add ide_set_pio_mode()/ide_set_dma_mode() helpers and convert all
direct ->set_pio_mode/->speedproc users to use these helpers.
* Move ide_config_drive_speed() calls from ->set_pio_mode/->speedproc
methods to callers.
* Rename ->speedproc method to ->set_dma_mode, make it void and update
all implementations accordingly.
* Update ide_set_xfer_rate() comments.
* Unexport ide_config_drive_speed().
v2:
* Fix issues noticed by Sergei:
- export ide_set_dma_mode() instead of moving ->set_pio_mode abuse wrt
to setting DMA modes from sc1200_set_pio_mode() to do_special()
- check IDE_HFLAG_NO_SET_MODE in ide_tune_dma()
- check for (hwif->set_pio_mode) == NULL in ide_set_pio_mode()
- check for (hwif->set_dma_mode) == NULL in ide_set_dma_mode()
- return -1 from ide_set_{pio,dma}_mode() if ->set_{pio,dma}_mode == NULL
- don't set ->set_{pio,dma}_mode on it821x in "smart" mode
- fix build problem in pmac.c
- minor fixes in au1xxx-ide.c/cs5530.c/siimage.c
- improve patch description
Changes in behavior caused by this patch:
- HDIO_SET_PIO_MODE ioctl would now return -ENOSYS for attempts to change
PIO mode if it821x controller is in "smart" mode
- removal of two debugging printk-s (from cs5530.c and sc1200.c)
- transfer modes 0x00-0x07 passed from user space may be programmed twice on
the device (not really an issue since 0x00 is not supported correctly by
any host driver ATM, 0x01 is not supported at all and 0x02-0x07 are invalid)
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
2007-10-13 09:47:51 -06:00
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* amd_set_drive() computes timing values and configures the chipset
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* to a desired transfer mode. It also can be called by upper layers.
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2005-04-16 16:20:36 -06:00
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*/
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2010-01-19 02:45:29 -07:00
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static void amd_set_drive(ide_hwif_t *hwif, ide_drive_t *drive)
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2005-04-16 16:20:36 -06:00
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{
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2008-02-01 15:09:31 -07:00
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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2009-01-06 09:20:54 -07:00
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ide_drive_t *peer = ide_get_pair_dev(drive);
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2005-04-16 16:20:36 -06:00
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struct ide_timing t, p;
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int T, UT;
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2008-02-01 15:09:30 -07:00
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u8 udma_mask = hwif->ultra_mask;
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2010-01-19 02:45:29 -07:00
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const u8 speed = drive->dma_mode;
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2005-04-16 16:20:36 -06:00
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T = 1000000000 / amd_clock;
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2008-02-01 15:09:30 -07:00
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UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);
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2005-04-16 16:20:36 -06:00
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ide_timing_compute(drive, speed, &t, T, UT);
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2009-01-06 09:20:54 -07:00
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if (peer) {
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2010-01-18 00:21:33 -07:00
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ide_timing_compute(peer, peer->pio_mode, &p, T, UT);
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2005-04-16 16:20:36 -06:00
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ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
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}
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if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
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if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
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2008-02-01 15:09:31 -07:00
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amd_set_speed(dev, drive->dn, udma_mask, &t);
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2005-04-16 16:20:36 -06:00
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}
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/*
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2007-10-11 15:54:00 -06:00
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* amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
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2005-04-16 16:20:36 -06:00
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*/
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2010-01-19 02:44:41 -07:00
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static void amd_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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2005-04-16 16:20:36 -06:00
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{
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2010-01-19 02:45:29 -07:00
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drive->dma_mode = drive->pio_mode;
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amd_set_drive(hwif, drive);
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2005-04-16 16:20:36 -06:00
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}
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2008-10-10 14:39:32 -06:00
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static void amd7409_cable_detect(struct pci_dev *dev)
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2008-02-01 15:09:30 -07:00
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{
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/* no host side cable detection */
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amd_80w = 0x03;
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}
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2005-04-16 16:20:36 -06:00
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2008-10-10 14:39:32 -06:00
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static void amd7411_cable_detect(struct pci_dev *dev)
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2005-04-16 16:20:36 -06:00
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{
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int i;
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2008-02-01 15:09:30 -07:00
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u32 u = 0;
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u8 t = 0, offset = amd_offset(dev);
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pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t);
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pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u);
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amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
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for (i = 24; i >= 0; i -= 8)
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if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
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2008-07-24 14:53:33 -06:00
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printk(KERN_WARNING DRV_NAME " %s: BIOS didn't set "
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"cable bits correctly. Enabling workaround.\n",
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pci_name(dev));
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2008-02-01 15:09:30 -07:00
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amd_80w |= (1 << (1 - (i >> 4)));
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}
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}
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2005-04-16 16:20:36 -06:00
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/*
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2008-02-01 15:09:30 -07:00
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* The initialization callback. Initialize drive independent registers.
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2005-04-16 16:20:36 -06:00
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*/
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2009-03-24 16:22:53 -06:00
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static int init_chipset_amd74xx(struct pci_dev *dev)
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2008-02-01 15:09:30 -07:00
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{
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u8 t = 0, offset = amd_offset(dev);
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2005-04-16 16:20:36 -06:00
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/*
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* Check 80-wire cable presence.
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*/
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2008-02-01 15:09:30 -07:00
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if (dev->vendor == PCI_VENDOR_ID_AMD &&
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dev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
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; /* no UDMA > 2 */
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else if (dev->vendor == PCI_VENDOR_ID_AMD &&
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dev->device == PCI_DEVICE_ID_AMD_VIPER_7409)
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2008-07-24 14:53:33 -06:00
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amd7409_cable_detect(dev);
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2008-02-01 15:09:30 -07:00
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else
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2008-07-24 14:53:33 -06:00
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amd7411_cable_detect(dev);
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2005-04-16 16:20:36 -06:00
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/*
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* Take care of prefetch & postwrite.
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*/
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2008-02-01 15:09:30 -07:00
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pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t);
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/*
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* Check for broken FIFO support.
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*/
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if (dev->vendor == PCI_VENDOR_ID_AMD &&
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2009-02-25 12:28:22 -07:00
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dev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
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2008-02-01 15:09:30 -07:00
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t &= 0x0f;
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else
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t |= 0xf0;
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pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t);
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2005-04-16 16:20:36 -06:00
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2009-03-24 16:22:53 -06:00
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return 0;
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2005-04-16 16:20:36 -06:00
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}
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2008-08-05 10:17:04 -06:00
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static u8 amd_cable_detect(ide_hwif_t *hwif)
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2008-02-02 11:56:31 -07:00
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{
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if ((amd_80w >> hwif->channel) & 1)
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return ATA_CBL_PATA80;
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else
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return ATA_CBL_PATA40;
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}
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2008-04-26 14:25:14 -06:00
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static const struct ide_port_ops amd_port_ops = {
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.set_pio_mode = amd_set_pio_mode,
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.set_dma_mode = amd_set_drive,
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.cable_detect = amd_cable_detect,
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};
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2007-10-19 16:32:30 -06:00
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#define IDE_HFLAGS_AMD \
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(IDE_HFLAG_PIO_NO_BLACKLIST | \
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IDE_HFLAG_POST_SET_MODE | \
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IDE_HFLAG_IO_32BIT | \
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2008-04-26 09:36:35 -06:00
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IDE_HFLAG_UNMASK_IRQS)
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2007-10-19 16:32:30 -06:00
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2008-07-24 14:53:32 -06:00
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#define DECLARE_AMD_DEV(swdma, udma) \
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2005-04-16 16:20:36 -06:00
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{ \
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2008-07-24 14:53:32 -06:00
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.name = DRV_NAME, \
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2005-04-16 16:20:36 -06:00
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.init_chipset = init_chipset_amd74xx, \
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.enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
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2008-04-26 14:25:14 -06:00
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.port_ops = &amd_port_ops, \
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2007-10-19 16:32:30 -06:00
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.host_flags = IDE_HFLAGS_AMD, \
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2007-07-19 17:11:59 -06:00
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.pio_mask = ATA_PIO5, \
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2008-02-01 15:09:30 -07:00
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.swdma_mask = swdma, \
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2007-10-18 16:30:07 -06:00
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.mwdma_mask = ATA_MWDMA2, \
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2008-02-01 15:09:30 -07:00
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.udma_mask = udma, \
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2005-04-16 16:20:36 -06:00
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}
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2008-07-24 14:53:32 -06:00
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#define DECLARE_NV_DEV(udma) \
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2005-04-16 16:20:36 -06:00
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{ \
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2008-07-24 14:53:32 -06:00
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.name = DRV_NAME, \
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2005-04-16 16:20:36 -06:00
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.init_chipset = init_chipset_amd74xx, \
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.enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
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2008-04-26 14:25:14 -06:00
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.port_ops = &amd_port_ops, \
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2007-10-19 16:32:30 -06:00
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.host_flags = IDE_HFLAGS_AMD, \
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2007-07-19 17:11:59 -06:00
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.pio_mask = ATA_PIO5, \
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2007-10-18 16:30:07 -06:00
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.swdma_mask = ATA_SWDMA2, \
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.mwdma_mask = ATA_MWDMA2, \
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2008-02-01 15:09:30 -07:00
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.udma_mask = udma, \
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2005-04-16 16:20:36 -06:00
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}
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2007-10-19 16:32:34 -06:00
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static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
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2008-07-24 14:53:32 -06:00
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/* 0: AMD7401 */ DECLARE_AMD_DEV(0x00, ATA_UDMA2),
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/* 1: AMD7409 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA4),
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/* 2: AMD7411/7441 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
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/* 3: AMD8111 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA6),
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/* 4: NFORCE */ DECLARE_NV_DEV(ATA_UDMA5),
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/* 5: >= NFORCE2 */ DECLARE_NV_DEV(ATA_UDMA6),
|
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|
|
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/* 6: AMD5536 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
|
2005-04-16 16:20:36 -06:00
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|
};
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|
|
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|
|
|
static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|
|
|
{
|
2008-02-01 15:09:30 -07:00
|
|
|
struct ide_port_info d;
|
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|
|
u8 idx = id->driver_data;
|
|
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|
|
d = amd74xx_chipsets[idx];
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check for bad SWDMA and incorrectly wired Serenade mainboards.
|
|
|
|
*/
|
|
|
|
if (idx == 1) {
|
|
|
|
if (dev->revision <= 7)
|
|
|
|
d.swdma_mask = 0;
|
2008-02-01 15:09:30 -07:00
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|
d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
|
2008-07-24 14:53:32 -06:00
|
|
|
} else if (idx == 3) {
|
2008-02-01 15:09:30 -07:00
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|
|
if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
|
|
|
|
dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
|
|
|
|
d.udma_mask = ATA_UDMA5;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
2008-02-01 15:09:30 -07:00
|
|
|
|
2008-12-02 12:40:03 -07:00
|
|
|
/*
|
|
|
|
* It seems that on some nVidia controllers using AltStatus
|
|
|
|
* register can be unreliable so default to Status register
|
|
|
|
* if the device is in Compatibility Mode.
|
|
|
|
*/
|
|
|
|
if (dev->vendor == PCI_VENDOR_ID_NVIDIA &&
|
|
|
|
ide_pci_is_in_compatibility_mode(dev))
|
|
|
|
d.host_flags |= IDE_HFLAG_BROKEN_ALTSTATUS;
|
|
|
|
|
2008-07-24 14:53:31 -06:00
|
|
|
printk(KERN_INFO "%s %s: UDMA%s controller\n",
|
|
|
|
d.name, pci_name(dev), amd_dma[fls(d.udma_mask) - 1]);
|
2008-02-01 15:09:30 -07:00
|
|
|
|
2008-07-24 14:53:17 -06:00
|
|
|
/*
|
|
|
|
* Determine the system bus clock.
|
|
|
|
*/
|
|
|
|
amd_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;
|
|
|
|
|
|
|
|
switch (amd_clock) {
|
|
|
|
case 33000: amd_clock = 33333; break;
|
|
|
|
case 37000: amd_clock = 37500; break;
|
|
|
|
case 41000: amd_clock = 41666; break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (amd_clock < 20000 || amd_clock > 50000) {
|
|
|
|
printk(KERN_WARNING "%s: User given PCI clock speed impossible"
|
|
|
|
" (%d), using 33 MHz instead.\n",
|
|
|
|
d.name, amd_clock);
|
|
|
|
amd_clock = 33333;
|
|
|
|
}
|
|
|
|
|
2008-07-24 14:53:14 -06:00
|
|
|
return ide_pci_init_one(dev, &d, NULL);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2007-10-16 14:29:56 -06:00
|
|
|
static const struct pci_device_id amd74xx_pci_tbl[] = {
|
|
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
|
|
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
|
|
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 },
|
2008-07-24 14:53:32 -06:00
|
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 2 },
|
|
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 3 },
|
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 4 },
|
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 5 },
|
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 5 },
|
2005-04-16 16:20:36 -06:00
|
|
|
#ifdef CONFIG_BLK_DEV_IDE_SATA
|
2008-07-24 14:53:32 -06:00
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 5 },
|
2005-04-16 16:20:36 -06:00
|
|
|
#endif
|
2008-07-24 14:53:32 -06:00
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 5 },
|
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 5 },
|
2005-04-16 16:20:36 -06:00
|
|
|
#ifdef CONFIG_BLK_DEV_IDE_SATA
|
2008-07-24 14:53:32 -06:00
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 5 },
|
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 5 },
|
2005-04-16 16:20:36 -06:00
|
|
|
#endif
|
2008-07-24 14:53:32 -06:00
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 5 },
|
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 5 },
|
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 5 },
|
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 5 },
|
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 5 },
|
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 5 },
|
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 5 },
|
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 5 },
|
|
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 5 },
|
|
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 6 },
|
2005-04-16 16:20:36 -06:00
|
|
|
{ 0, },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
|
|
|
|
|
2008-10-13 13:39:41 -06:00
|
|
|
static struct pci_driver amd74xx_pci_driver = {
|
2005-04-16 16:20:36 -06:00
|
|
|
.name = "AMD_IDE",
|
|
|
|
.id_table = amd74xx_pci_tbl,
|
|
|
|
.probe = amd74xx_probe,
|
2008-07-24 14:53:19 -06:00
|
|
|
.remove = ide_pci_remove,
|
2008-10-10 14:39:32 -06:00
|
|
|
.suspend = ide_pci_suspend,
|
|
|
|
.resume = ide_pci_resume,
|
2005-04-16 16:20:36 -06:00
|
|
|
};
|
|
|
|
|
2007-01-27 05:46:56 -07:00
|
|
|
static int __init amd74xx_ide_init(void)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
2008-10-13 13:39:41 -06:00
|
|
|
return ide_pci_register_driver(&amd74xx_pci_driver);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2008-07-24 14:53:19 -06:00
|
|
|
static void __exit amd74xx_ide_exit(void)
|
|
|
|
{
|
2008-10-13 13:39:41 -06:00
|
|
|
pci_unregister_driver(&amd74xx_pci_driver);
|
2008-07-24 14:53:19 -06:00
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
module_init(amd74xx_ide_init);
|
2008-07-24 14:53:19 -06:00
|
|
|
module_exit(amd74xx_ide_exit);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2010-01-18 00:18:17 -07:00
|
|
|
MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz");
|
2005-04-16 16:20:36 -06:00
|
|
|
MODULE_DESCRIPTION("AMD PCI IDE driver");
|
|
|
|
MODULE_LICENSE("GPL");
|