2005-04-16 16:20:36 -06:00
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/*
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* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
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* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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2008-11-02 13:40:08 -07:00
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* Copyright (C) 2003 Red Hat
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2007-03-03 09:48:53 -07:00
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* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
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2005-04-16 16:20:36 -06:00
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*
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* May be copied or modified under the terms of the GNU General Public License
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*
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2008-02-01 15:09:30 -07:00
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* Documentation:
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2005-04-16 16:20:36 -06:00
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*
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* Publically available from Intel web site. Errata documentation
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* is also publically available. As an aide to anyone hacking on this
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* driver the list of errata that are relevant is below.going back to
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* PIIX4. Older device documentation is now a bit tricky to find.
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*
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* Errata of note:
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*
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* Unfixable
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* PIIX4 errata #9 - Only on ultra obscure hw
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* ICH3 errata #13 - Not observed to affect real hw
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* by Intel
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*
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* Things we must deal with
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* PIIX4 errata #10 - BM IDE hang with non UDMA
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* (must stop/start dma to recover)
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* 440MX errata #15 - As PIIX4 errata #10
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* PIIX4 errata #15 - Must not read control registers
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* during a PIO transfer
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* 440MX errata #13 - As PIIX4 errata #15
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* ICH2 errata #21 - DMA mode 0 doesn't work right
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* ICH0/1 errata #55 - As ICH2 errata #21
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* ICH2 spec c #9 - Extra operations needed to handle
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* drive hotswap [NOT YET SUPPORTED]
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* ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
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* and must be dword aligned
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* ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
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*
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* Should have been BIOS fixed:
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* 450NX: errata #19 - DMA hangs on old 450NX
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* 450NX: errata #20 - DMA hangs on old 450NX
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* 450NX: errata #25 - Corruption with DMA on old 450NX
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* ICH3 errata #15 - IDE deadlock under high load
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* (BIOS must set dev 31 fn 0 bit 23)
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* ICH3 errata #18 - Don't use native mode
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <linux/init.h>
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#include <asm/io.h>
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2008-07-24 14:53:32 -06:00
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#define DRV_NAME "piix"
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2005-04-16 16:20:36 -06:00
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static int no_piix_dma;
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/**
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ide: move ide_config_drive_speed() calls to upper layers (take 2)
* Convert {ide_hwif_t,ide_pci_device_t}->host_flag to be u16.
* Add IDE_HFLAG_POST_SET_MODE host flag to indicate the need to program
the host for the transfer mode after programming the device. Set it
in au1xxx-ide, amd74xx, cs5530, cs5535, pdc202xx_new, sc1200, pmac
and via82cxxx host drivers.
* Add IDE_HFLAG_NO_SET_MODE host flag to indicate the need to completely
skip programming of host/device for the transfer mode ("smart" hosts).
Set it in it821x host driver and check it in ide_tune_dma().
* Add ide_set_pio_mode()/ide_set_dma_mode() helpers and convert all
direct ->set_pio_mode/->speedproc users to use these helpers.
* Move ide_config_drive_speed() calls from ->set_pio_mode/->speedproc
methods to callers.
* Rename ->speedproc method to ->set_dma_mode, make it void and update
all implementations accordingly.
* Update ide_set_xfer_rate() comments.
* Unexport ide_config_drive_speed().
v2:
* Fix issues noticed by Sergei:
- export ide_set_dma_mode() instead of moving ->set_pio_mode abuse wrt
to setting DMA modes from sc1200_set_pio_mode() to do_special()
- check IDE_HFLAG_NO_SET_MODE in ide_tune_dma()
- check for (hwif->set_pio_mode) == NULL in ide_set_pio_mode()
- check for (hwif->set_dma_mode) == NULL in ide_set_dma_mode()
- return -1 from ide_set_{pio,dma}_mode() if ->set_{pio,dma}_mode == NULL
- don't set ->set_{pio,dma}_mode on it821x in "smart" mode
- fix build problem in pmac.c
- minor fixes in au1xxx-ide.c/cs5530.c/siimage.c
- improve patch description
Changes in behavior caused by this patch:
- HDIO_SET_PIO_MODE ioctl would now return -ENOSYS for attempts to change
PIO mode if it821x controller is in "smart" mode
- removal of two debugging printk-s (from cs5530.c and sc1200.c)
- transfer modes 0x00-0x07 passed from user space may be programmed twice on
the device (not really an issue since 0x00 is not supported correctly by
any host driver ATM, 0x01 is not supported at all and 0x02-0x07 are invalid)
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
2007-10-13 09:47:51 -06:00
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* piix_set_pio_mode - set host controller for PIO mode
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* @drive: drive
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* @pio: PIO mode number
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2005-04-16 16:20:36 -06:00
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*
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2007-03-03 09:48:53 -07:00
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* Set the interface PIO mode based upon the settings done by AMI BIOS.
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2005-04-16 16:20:36 -06:00
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*/
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ide: move ide_config_drive_speed() calls to upper layers (take 2)
* Convert {ide_hwif_t,ide_pci_device_t}->host_flag to be u16.
* Add IDE_HFLAG_POST_SET_MODE host flag to indicate the need to program
the host for the transfer mode after programming the device. Set it
in au1xxx-ide, amd74xx, cs5530, cs5535, pdc202xx_new, sc1200, pmac
and via82cxxx host drivers.
* Add IDE_HFLAG_NO_SET_MODE host flag to indicate the need to completely
skip programming of host/device for the transfer mode ("smart" hosts).
Set it in it821x host driver and check it in ide_tune_dma().
* Add ide_set_pio_mode()/ide_set_dma_mode() helpers and convert all
direct ->set_pio_mode/->speedproc users to use these helpers.
* Move ide_config_drive_speed() calls from ->set_pio_mode/->speedproc
methods to callers.
* Rename ->speedproc method to ->set_dma_mode, make it void and update
all implementations accordingly.
* Update ide_set_xfer_rate() comments.
* Unexport ide_config_drive_speed().
v2:
* Fix issues noticed by Sergei:
- export ide_set_dma_mode() instead of moving ->set_pio_mode abuse wrt
to setting DMA modes from sc1200_set_pio_mode() to do_special()
- check IDE_HFLAG_NO_SET_MODE in ide_tune_dma()
- check for (hwif->set_pio_mode) == NULL in ide_set_pio_mode()
- check for (hwif->set_dma_mode) == NULL in ide_set_dma_mode()
- return -1 from ide_set_{pio,dma}_mode() if ->set_{pio,dma}_mode == NULL
- don't set ->set_{pio,dma}_mode on it821x in "smart" mode
- fix build problem in pmac.c
- minor fixes in au1xxx-ide.c/cs5530.c/siimage.c
- improve patch description
Changes in behavior caused by this patch:
- HDIO_SET_PIO_MODE ioctl would now return -ENOSYS for attempts to change
PIO mode if it821x controller is in "smart" mode
- removal of two debugging printk-s (from cs5530.c and sc1200.c)
- transfer modes 0x00-0x07 passed from user space may be programmed twice on
the device (not really an issue since 0x00 is not supported correctly by
any host driver ATM, 0x01 is not supported at all and 0x02-0x07 are invalid)
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
2007-10-13 09:47:51 -06:00
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static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
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2005-04-16 16:20:36 -06:00
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{
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2009-01-06 09:20:52 -07:00
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ide_hwif_t *hwif = drive->hwif;
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2008-02-01 15:09:31 -07:00
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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2007-02-07 10:18:28 -07:00
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int is_slave = drive->dn & 1;
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2005-04-16 16:20:36 -06:00
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int master_port = hwif->channel ? 0x42 : 0x40;
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int slave_port = 0x44;
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unsigned long flags;
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u16 master_data;
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u8 slave_data;
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2006-06-26 01:26:12 -06:00
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static DEFINE_SPINLOCK(tune_lock);
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[PATCH] ide: backport piix fixes from libata into the legacy driver
There are three flags being set by default by the PIIX driver for speeds >
PIO 1, and one not being cleared properly on fallback to PIO0. The most
important one is the prefetch/post write control which only works for ATA
and can do bad things with ATAPI.
The patch does its best to set the flags correctly for drivers/ide. Its
not 100% perfect but its closer than the original. 100% perfect requires
proper IORDY handling but this isn't critical (and its not right in libata
either .. yet)
Sergei Shtylyov <sshtylyov@ru.mvista.com> said:
> + { 0, 0 },
> + { 0, 0 },
> + { 1, 0 },
> + { 2, 1 },
> + { 2, 3 }, };
>
> pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
BTW, there's quite obvious error here which leads to access outside of
timings[] if somebody passes PIO mode 5 (or autotuning code finds out that
drive supports PIO mode 5). Could have been fixed while at it... Those drives
should be rare, though...
> + }
> master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
> }
> pci_write_config_word(dev, master_port, master_data);
Actually, there's one more serious issue with piix_tune_drive() -- it
doesn't actually set the drive's own transfer mode.
Signed-off-by: Alan Cox <alan@redhat.com>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-10-03 02:14:23 -06:00
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int control = 0;
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2006-06-26 01:26:12 -06:00
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2007-02-07 10:18:28 -07:00
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/* ISP RTC */
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[PATCH] ide: backport piix fixes from libata into the legacy driver
There are three flags being set by default by the PIIX driver for speeds >
PIO 1, and one not being cleared properly on fallback to PIO0. The most
important one is the prefetch/post write control which only works for ATA
and can do bad things with ATAPI.
The patch does its best to set the flags correctly for drivers/ide. Its
not 100% perfect but its closer than the original. 100% perfect requires
proper IORDY handling but this isn't critical (and its not right in libata
either .. yet)
Sergei Shtylyov <sshtylyov@ru.mvista.com> said:
> + { 0, 0 },
> + { 0, 0 },
> + { 1, 0 },
> + { 2, 1 },
> + { 2, 3 }, };
>
> pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
BTW, there's quite obvious error here which leads to access outside of
timings[] if somebody passes PIO mode 5 (or autotuning code finds out that
drive supports PIO mode 5). Could have been fixed while at it... Those drives
should be rare, though...
> + }
> master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
> }
> pci_write_config_word(dev, master_port, master_data);
Actually, there's one more serious issue with piix_tune_drive() -- it
doesn't actually set the drive's own transfer mode.
Signed-off-by: Alan Cox <alan@redhat.com>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-10-03 02:14:23 -06:00
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static const u8 timings[][2]= {
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{ 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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2005-04-16 16:20:36 -06:00
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2006-06-26 01:26:12 -06:00
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/*
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* Master vs slave is synchronized above us but the slave register is
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* shared by the two hwifs so the corner case of two slave timeouts in
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* parallel must be locked.
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*/
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spin_lock_irqsave(&tune_lock, flags);
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2005-04-16 16:20:36 -06:00
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pci_read_config_word(dev, master_port, &master_data);
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[PATCH] ide: backport piix fixes from libata into the legacy driver
There are three flags being set by default by the PIIX driver for speeds >
PIO 1, and one not being cleared properly on fallback to PIO0. The most
important one is the prefetch/post write control which only works for ATA
and can do bad things with ATAPI.
The patch does its best to set the flags correctly for drivers/ide. Its
not 100% perfect but its closer than the original. 100% perfect requires
proper IORDY handling but this isn't critical (and its not right in libata
either .. yet)
Sergei Shtylyov <sshtylyov@ru.mvista.com> said:
> + { 0, 0 },
> + { 0, 0 },
> + { 1, 0 },
> + { 2, 1 },
> + { 2, 3 }, };
>
> pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
BTW, there's quite obvious error here which leads to access outside of
timings[] if somebody passes PIO mode 5 (or autotuning code finds out that
drive supports PIO mode 5). Could have been fixed while at it... Those drives
should be rare, though...
> + }
> master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
> }
> pci_write_config_word(dev, master_port, master_data);
Actually, there's one more serious issue with piix_tune_drive() -- it
doesn't actually set the drive's own transfer mode.
Signed-off-by: Alan Cox <alan@redhat.com>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-10-03 02:14:23 -06:00
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2007-02-07 10:18:28 -07:00
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if (pio > 1)
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[PATCH] ide: backport piix fixes from libata into the legacy driver
There are three flags being set by default by the PIIX driver for speeds >
PIO 1, and one not being cleared properly on fallback to PIO0. The most
important one is the prefetch/post write control which only works for ATA
and can do bad things with ATAPI.
The patch does its best to set the flags correctly for drivers/ide. Its
not 100% perfect but its closer than the original. 100% perfect requires
proper IORDY handling but this isn't critical (and its not right in libata
either .. yet)
Sergei Shtylyov <sshtylyov@ru.mvista.com> said:
> + { 0, 0 },
> + { 0, 0 },
> + { 1, 0 },
> + { 2, 1 },
> + { 2, 3 }, };
>
> pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
BTW, there's quite obvious error here which leads to access outside of
timings[] if somebody passes PIO mode 5 (or autotuning code finds out that
drive supports PIO mode 5). Could have been fixed while at it... Those drives
should be rare, though...
> + }
> master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
> }
> pci_write_config_word(dev, master_port, master_data);
Actually, there's one more serious issue with piix_tune_drive() -- it
doesn't actually set the drive's own transfer mode.
Signed-off-by: Alan Cox <alan@redhat.com>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-10-03 02:14:23 -06:00
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control |= 1; /* Programmable timing on */
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if (drive->media == ide_disk)
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control |= 4; /* Prefetch, post write */
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2009-06-15 10:52:53 -06:00
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if (ide_pio_need_iordy(drive, pio))
|
[PATCH] ide: backport piix fixes from libata into the legacy driver
There are three flags being set by default by the PIIX driver for speeds >
PIO 1, and one not being cleared properly on fallback to PIO0. The most
important one is the prefetch/post write control which only works for ATA
and can do bad things with ATAPI.
The patch does its best to set the flags correctly for drivers/ide. Its
not 100% perfect but its closer than the original. 100% perfect requires
proper IORDY handling but this isn't critical (and its not right in libata
either .. yet)
Sergei Shtylyov <sshtylyov@ru.mvista.com> said:
> + { 0, 0 },
> + { 0, 0 },
> + { 1, 0 },
> + { 2, 1 },
> + { 2, 3 }, };
>
> pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
BTW, there's quite obvious error here which leads to access outside of
timings[] if somebody passes PIO mode 5 (or autotuning code finds out that
drive supports PIO mode 5). Could have been fixed while at it... Those drives
should be rare, though...
> + }
> master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
> }
> pci_write_config_word(dev, master_port, master_data);
Actually, there's one more serious issue with piix_tune_drive() -- it
doesn't actually set the drive's own transfer mode.
Signed-off-by: Alan Cox <alan@redhat.com>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-10-03 02:14:23 -06:00
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control |= 2; /* IORDY */
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2005-04-16 16:20:36 -06:00
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if (is_slave) {
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2007-02-07 10:18:28 -07:00
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master_data |= 0x4000;
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master_data &= ~0x0070;
|
[PATCH] ide: backport piix fixes from libata into the legacy driver
There are three flags being set by default by the PIIX driver for speeds >
PIO 1, and one not being cleared properly on fallback to PIO0. The most
important one is the prefetch/post write control which only works for ATA
and can do bad things with ATAPI.
The patch does its best to set the flags correctly for drivers/ide. Its
not 100% perfect but its closer than the original. 100% perfect requires
proper IORDY handling but this isn't critical (and its not right in libata
either .. yet)
Sergei Shtylyov <sshtylyov@ru.mvista.com> said:
> + { 0, 0 },
> + { 0, 0 },
> + { 1, 0 },
> + { 2, 1 },
> + { 2, 3 }, };
>
> pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
BTW, there's quite obvious error here which leads to access outside of
timings[] if somebody passes PIO mode 5 (or autotuning code finds out that
drive supports PIO mode 5). Could have been fixed while at it... Those drives
should be rare, though...
> + }
> master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
> }
> pci_write_config_word(dev, master_port, master_data);
Actually, there's one more serious issue with piix_tune_drive() -- it
doesn't actually set the drive's own transfer mode.
Signed-off-by: Alan Cox <alan@redhat.com>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-10-03 02:14:23 -06:00
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if (pio > 1) {
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2007-03-03 09:48:53 -07:00
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/* Set PPE, IE and TIME */
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master_data |= control << 4;
|
[PATCH] ide: backport piix fixes from libata into the legacy driver
There are three flags being set by default by the PIIX driver for speeds >
PIO 1, and one not being cleared properly on fallback to PIO0. The most
important one is the prefetch/post write control which only works for ATA
and can do bad things with ATAPI.
The patch does its best to set the flags correctly for drivers/ide. Its
not 100% perfect but its closer than the original. 100% perfect requires
proper IORDY handling but this isn't critical (and its not right in libata
either .. yet)
Sergei Shtylyov <sshtylyov@ru.mvista.com> said:
> + { 0, 0 },
> + { 0, 0 },
> + { 1, 0 },
> + { 2, 1 },
> + { 2, 3 }, };
>
> pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
BTW, there's quite obvious error here which leads to access outside of
timings[] if somebody passes PIO mode 5 (or autotuning code finds out that
drive supports PIO mode 5). Could have been fixed while at it... Those drives
should be rare, though...
> + }
> master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
> }
> pci_write_config_word(dev, master_port, master_data);
Actually, there's one more serious issue with piix_tune_drive() -- it
doesn't actually set the drive's own transfer mode.
Signed-off-by: Alan Cox <alan@redhat.com>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-10-03 02:14:23 -06:00
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
pci_read_config_byte(dev, slave_port, &slave_data);
|
2007-03-03 09:48:53 -07:00
|
|
|
slave_data &= hwif->channel ? 0x0f : 0xf0;
|
|
|
|
slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
|
|
|
|
(hwif->channel ? 4 : 0);
|
2005-04-16 16:20:36 -06:00
|
|
|
} else {
|
2007-02-07 10:18:28 -07:00
|
|
|
master_data &= ~0x3307;
|
[PATCH] ide: backport piix fixes from libata into the legacy driver
There are three flags being set by default by the PIIX driver for speeds >
PIO 1, and one not being cleared properly on fallback to PIO0. The most
important one is the prefetch/post write control which only works for ATA
and can do bad things with ATAPI.
The patch does its best to set the flags correctly for drivers/ide. Its
not 100% perfect but its closer than the original. 100% perfect requires
proper IORDY handling but this isn't critical (and its not right in libata
either .. yet)
Sergei Shtylyov <sshtylyov@ru.mvista.com> said:
> + { 0, 0 },
> + { 0, 0 },
> + { 1, 0 },
> + { 2, 1 },
> + { 2, 3 }, };
>
> pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
BTW, there's quite obvious error here which leads to access outside of
timings[] if somebody passes PIO mode 5 (or autotuning code finds out that
drive supports PIO mode 5). Could have been fixed while at it... Those drives
should be rare, though...
> + }
> master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
> }
> pci_write_config_word(dev, master_port, master_data);
Actually, there's one more serious issue with piix_tune_drive() -- it
doesn't actually set the drive's own transfer mode.
Signed-off-by: Alan Cox <alan@redhat.com>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-10-03 02:14:23 -06:00
|
|
|
if (pio > 1) {
|
2005-04-16 16:20:36 -06:00
|
|
|
/* enable PPE, IE and TIME */
|
2007-03-03 09:48:53 -07:00
|
|
|
master_data |= control;
|
[PATCH] ide: backport piix fixes from libata into the legacy driver
There are three flags being set by default by the PIIX driver for speeds >
PIO 1, and one not being cleared properly on fallback to PIO0. The most
important one is the prefetch/post write control which only works for ATA
and can do bad things with ATAPI.
The patch does its best to set the flags correctly for drivers/ide. Its
not 100% perfect but its closer than the original. 100% perfect requires
proper IORDY handling but this isn't critical (and its not right in libata
either .. yet)
Sergei Shtylyov <sshtylyov@ru.mvista.com> said:
> + { 0, 0 },
> + { 0, 0 },
> + { 1, 0 },
> + { 2, 1 },
> + { 2, 3 }, };
>
> pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
BTW, there's quite obvious error here which leads to access outside of
timings[] if somebody passes PIO mode 5 (or autotuning code finds out that
drive supports PIO mode 5). Could have been fixed while at it... Those drives
should be rare, though...
> + }
> master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
> }
> pci_write_config_word(dev, master_port, master_data);
Actually, there's one more serious issue with piix_tune_drive() -- it
doesn't actually set the drive's own transfer mode.
Signed-off-by: Alan Cox <alan@redhat.com>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-10-03 02:14:23 -06:00
|
|
|
}
|
2007-03-03 09:48:53 -07:00
|
|
|
master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
pci_write_config_word(dev, master_port, master_data);
|
|
|
|
if (is_slave)
|
|
|
|
pci_write_config_byte(dev, slave_port, slave_data);
|
2006-06-26 01:26:12 -06:00
|
|
|
spin_unlock_irqrestore(&tune_lock, flags);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2007-03-03 09:48:53 -07:00
|
|
|
/**
|
ide: move ide_config_drive_speed() calls to upper layers (take 2)
* Convert {ide_hwif_t,ide_pci_device_t}->host_flag to be u16.
* Add IDE_HFLAG_POST_SET_MODE host flag to indicate the need to program
the host for the transfer mode after programming the device. Set it
in au1xxx-ide, amd74xx, cs5530, cs5535, pdc202xx_new, sc1200, pmac
and via82cxxx host drivers.
* Add IDE_HFLAG_NO_SET_MODE host flag to indicate the need to completely
skip programming of host/device for the transfer mode ("smart" hosts).
Set it in it821x host driver and check it in ide_tune_dma().
* Add ide_set_pio_mode()/ide_set_dma_mode() helpers and convert all
direct ->set_pio_mode/->speedproc users to use these helpers.
* Move ide_config_drive_speed() calls from ->set_pio_mode/->speedproc
methods to callers.
* Rename ->speedproc method to ->set_dma_mode, make it void and update
all implementations accordingly.
* Update ide_set_xfer_rate() comments.
* Unexport ide_config_drive_speed().
v2:
* Fix issues noticed by Sergei:
- export ide_set_dma_mode() instead of moving ->set_pio_mode abuse wrt
to setting DMA modes from sc1200_set_pio_mode() to do_special()
- check IDE_HFLAG_NO_SET_MODE in ide_tune_dma()
- check for (hwif->set_pio_mode) == NULL in ide_set_pio_mode()
- check for (hwif->set_dma_mode) == NULL in ide_set_dma_mode()
- return -1 from ide_set_{pio,dma}_mode() if ->set_{pio,dma}_mode == NULL
- don't set ->set_{pio,dma}_mode on it821x in "smart" mode
- fix build problem in pmac.c
- minor fixes in au1xxx-ide.c/cs5530.c/siimage.c
- improve patch description
Changes in behavior caused by this patch:
- HDIO_SET_PIO_MODE ioctl would now return -ENOSYS for attempts to change
PIO mode if it821x controller is in "smart" mode
- removal of two debugging printk-s (from cs5530.c and sc1200.c)
- transfer modes 0x00-0x07 passed from user space may be programmed twice on
the device (not really an issue since 0x00 is not supported correctly by
any host driver ATM, 0x01 is not supported at all and 0x02-0x07 are invalid)
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
2007-10-13 09:47:51 -06:00
|
|
|
* piix_set_dma_mode - set host controller for DMA mode
|
|
|
|
* @drive: drive
|
|
|
|
* @speed: DMA mode
|
2005-04-16 16:20:36 -06:00
|
|
|
*
|
ide: move ide_config_drive_speed() calls to upper layers (take 2)
* Convert {ide_hwif_t,ide_pci_device_t}->host_flag to be u16.
* Add IDE_HFLAG_POST_SET_MODE host flag to indicate the need to program
the host for the transfer mode after programming the device. Set it
in au1xxx-ide, amd74xx, cs5530, cs5535, pdc202xx_new, sc1200, pmac
and via82cxxx host drivers.
* Add IDE_HFLAG_NO_SET_MODE host flag to indicate the need to completely
skip programming of host/device for the transfer mode ("smart" hosts).
Set it in it821x host driver and check it in ide_tune_dma().
* Add ide_set_pio_mode()/ide_set_dma_mode() helpers and convert all
direct ->set_pio_mode/->speedproc users to use these helpers.
* Move ide_config_drive_speed() calls from ->set_pio_mode/->speedproc
methods to callers.
* Rename ->speedproc method to ->set_dma_mode, make it void and update
all implementations accordingly.
* Update ide_set_xfer_rate() comments.
* Unexport ide_config_drive_speed().
v2:
* Fix issues noticed by Sergei:
- export ide_set_dma_mode() instead of moving ->set_pio_mode abuse wrt
to setting DMA modes from sc1200_set_pio_mode() to do_special()
- check IDE_HFLAG_NO_SET_MODE in ide_tune_dma()
- check for (hwif->set_pio_mode) == NULL in ide_set_pio_mode()
- check for (hwif->set_dma_mode) == NULL in ide_set_dma_mode()
- return -1 from ide_set_{pio,dma}_mode() if ->set_{pio,dma}_mode == NULL
- don't set ->set_{pio,dma}_mode on it821x in "smart" mode
- fix build problem in pmac.c
- minor fixes in au1xxx-ide.c/cs5530.c/siimage.c
- improve patch description
Changes in behavior caused by this patch:
- HDIO_SET_PIO_MODE ioctl would now return -ENOSYS for attempts to change
PIO mode if it821x controller is in "smart" mode
- removal of two debugging printk-s (from cs5530.c and sc1200.c)
- transfer modes 0x00-0x07 passed from user space may be programmed twice on
the device (not really an issue since 0x00 is not supported correctly by
any host driver ATM, 0x01 is not supported at all and 0x02-0x07 are invalid)
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
2007-10-13 09:47:51 -06:00
|
|
|
* Set a PIIX host controller to the desired DMA mode. This involves
|
|
|
|
* programming the right timing data into the PCI configuration space.
|
2005-04-16 16:20:36 -06:00
|
|
|
*/
|
2007-10-11 15:53:59 -06:00
|
|
|
|
ide: move ide_config_drive_speed() calls to upper layers (take 2)
* Convert {ide_hwif_t,ide_pci_device_t}->host_flag to be u16.
* Add IDE_HFLAG_POST_SET_MODE host flag to indicate the need to program
the host for the transfer mode after programming the device. Set it
in au1xxx-ide, amd74xx, cs5530, cs5535, pdc202xx_new, sc1200, pmac
and via82cxxx host drivers.
* Add IDE_HFLAG_NO_SET_MODE host flag to indicate the need to completely
skip programming of host/device for the transfer mode ("smart" hosts).
Set it in it821x host driver and check it in ide_tune_dma().
* Add ide_set_pio_mode()/ide_set_dma_mode() helpers and convert all
direct ->set_pio_mode/->speedproc users to use these helpers.
* Move ide_config_drive_speed() calls from ->set_pio_mode/->speedproc
methods to callers.
* Rename ->speedproc method to ->set_dma_mode, make it void and update
all implementations accordingly.
* Update ide_set_xfer_rate() comments.
* Unexport ide_config_drive_speed().
v2:
* Fix issues noticed by Sergei:
- export ide_set_dma_mode() instead of moving ->set_pio_mode abuse wrt
to setting DMA modes from sc1200_set_pio_mode() to do_special()
- check IDE_HFLAG_NO_SET_MODE in ide_tune_dma()
- check for (hwif->set_pio_mode) == NULL in ide_set_pio_mode()
- check for (hwif->set_dma_mode) == NULL in ide_set_dma_mode()
- return -1 from ide_set_{pio,dma}_mode() if ->set_{pio,dma}_mode == NULL
- don't set ->set_{pio,dma}_mode on it821x in "smart" mode
- fix build problem in pmac.c
- minor fixes in au1xxx-ide.c/cs5530.c/siimage.c
- improve patch description
Changes in behavior caused by this patch:
- HDIO_SET_PIO_MODE ioctl would now return -ENOSYS for attempts to change
PIO mode if it821x controller is in "smart" mode
- removal of two debugging printk-s (from cs5530.c and sc1200.c)
- transfer modes 0x00-0x07 passed from user space may be programmed twice on
the device (not really an issue since 0x00 is not supported correctly by
any host driver ATM, 0x01 is not supported at all and 0x02-0x07 are invalid)
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
2007-10-13 09:47:51 -06:00
|
|
|
static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
2009-01-06 09:20:52 -07:00
|
|
|
ide_hwif_t *hwif = drive->hwif;
|
2008-02-01 15:09:31 -07:00
|
|
|
struct pci_dev *dev = to_pci_dev(hwif->dev);
|
2005-04-16 16:20:36 -06:00
|
|
|
u8 maslave = hwif->channel ? 0x42 : 0x40;
|
|
|
|
int a_speed = 3 << (drive->dn * 4);
|
|
|
|
int u_flag = 1 << drive->dn;
|
|
|
|
int v_flag = 0x01 << drive->dn;
|
|
|
|
int w_flag = 0x10 << drive->dn;
|
|
|
|
int u_speed = 0;
|
|
|
|
int sitre;
|
|
|
|
u16 reg4042, reg4a;
|
2007-10-16 14:29:56 -06:00
|
|
|
u8 reg48, reg54, reg55;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
pci_read_config_word(dev, maslave, ®4042);
|
|
|
|
sitre = (reg4042 & 0x4000) ? 1 : 0;
|
|
|
|
pci_read_config_byte(dev, 0x48, ®48);
|
|
|
|
pci_read_config_word(dev, 0x4a, ®4a);
|
|
|
|
pci_read_config_byte(dev, 0x54, ®54);
|
|
|
|
pci_read_config_byte(dev, 0x55, ®55);
|
|
|
|
|
|
|
|
if (speed >= XFER_UDMA_0) {
|
2008-01-25 14:17:18 -07:00
|
|
|
u8 udma = speed - XFER_UDMA_0;
|
|
|
|
|
|
|
|
u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
if (!(reg48 & u_flag))
|
|
|
|
pci_write_config_byte(dev, 0x48, reg48 | u_flag);
|
|
|
|
if (speed == XFER_UDMA_5) {
|
|
|
|
pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
|
|
|
|
} else {
|
|
|
|
pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
|
|
|
|
}
|
|
|
|
if ((reg4a & a_speed) != u_speed)
|
|
|
|
pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
|
|
|
|
if (speed > XFER_UDMA_2) {
|
|
|
|
if (!(reg54 & v_flag))
|
|
|
|
pci_write_config_byte(dev, 0x54, reg54 | v_flag);
|
|
|
|
} else
|
|
|
|
pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
|
|
|
|
} else {
|
2007-10-16 14:29:54 -06:00
|
|
|
const u8 mwdma_to_pio[] = { 0, 3, 4 };
|
2007-10-16 14:29:56 -06:00
|
|
|
u8 pio;
|
2007-10-16 14:29:54 -06:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
if (reg48 & u_flag)
|
|
|
|
pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
|
|
|
|
if (reg4a & a_speed)
|
|
|
|
pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
|
|
|
|
if (reg54 & v_flag)
|
|
|
|
pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
|
|
|
|
if (reg55 & w_flag)
|
|
|
|
pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
|
2007-10-16 14:29:54 -06:00
|
|
|
|
|
|
|
if (speed >= XFER_MW_DMA_0)
|
|
|
|
pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
|
|
|
|
else
|
|
|
|
pio = 2; /* only SWDMA2 is allowed */
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2007-10-16 14:29:56 -06:00
|
|
|
piix_set_pio_mode(drive, pio);
|
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2007-10-18 16:30:10 -06:00
|
|
|
* init_chipset_ich - set up the ICH chipset
|
2007-02-16 18:40:21 -07:00
|
|
|
* @dev: PCI device to set up
|
|
|
|
*
|
2007-10-18 16:30:10 -06:00
|
|
|
* Initialize the PCI device as required. For the ICH this turns
|
|
|
|
* out to be nice and simple.
|
2007-02-16 18:40:21 -07:00
|
|
|
*/
|
|
|
|
|
2009-03-24 16:22:53 -06:00
|
|
|
static int init_chipset_ich(struct pci_dev *dev)
|
2007-02-16 18:40:21 -07:00
|
|
|
{
|
2007-10-18 16:30:10 -06:00
|
|
|
u32 extra = 0;
|
|
|
|
|
|
|
|
pci_read_config_dword(dev, 0x54, &extra);
|
|
|
|
pci_write_config_dword(dev, 0x54, extra | 0x400);
|
2007-02-16 18:40:21 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2008-10-13 13:39:42 -06:00
|
|
|
* ich_clear_irq - clear BMDMA status
|
|
|
|
* @drive: IDE drive
|
2007-02-16 18:40:21 -07:00
|
|
|
*
|
2008-10-13 13:39:42 -06:00
|
|
|
* ICHx contollers set DMA INTR no matter DMA or PIO.
|
|
|
|
* BMDMA status might need to be cleared even for
|
|
|
|
* PIO interrupts to prevent spurious/lost IRQ.
|
2007-02-16 18:40:21 -07:00
|
|
|
*/
|
2008-10-13 13:39:42 -06:00
|
|
|
static void ich_clear_irq(ide_drive_t *drive)
|
2007-02-16 18:40:21 -07:00
|
|
|
{
|
2009-01-06 09:20:52 -07:00
|
|
|
ide_hwif_t *hwif = drive->hwif;
|
2007-02-16 18:40:21 -07:00
|
|
|
u8 dma_stat;
|
|
|
|
|
2008-10-13 13:39:42 -06:00
|
|
|
/*
|
|
|
|
* ide_dma_end() needs BMDMA status for error checking.
|
|
|
|
* So, skip clearing BMDMA status here and leave it
|
|
|
|
* to ide_dma_end() if this is DMA interrupt.
|
|
|
|
*/
|
|
|
|
if (drive->waiting_for_dma || hwif->dma_base == 0)
|
|
|
|
return;
|
|
|
|
|
2007-02-16 18:40:21 -07:00
|
|
|
/* clear the INTR & ERROR bits */
|
2008-07-23 11:55:51 -06:00
|
|
|
dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
|
2007-02-16 18:40:21 -07:00
|
|
|
/* Should we force the bit as well ? */
|
2008-07-23 11:55:51 -06:00
|
|
|
outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
|
2007-02-16 18:40:21 -07:00
|
|
|
}
|
|
|
|
|
2007-07-09 15:17:58 -06:00
|
|
|
struct ich_laptop {
|
|
|
|
u16 device;
|
|
|
|
u16 subvendor;
|
|
|
|
u16 subdevice;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* List of laptops that use short cables rather than 80 wire
|
|
|
|
*/
|
|
|
|
|
|
|
|
static const struct ich_laptop ich_laptop[] = {
|
|
|
|
/* devid, subvendor, subdev */
|
2007-11-05 13:42:25 -07:00
|
|
|
{ 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
|
2007-07-09 15:17:58 -06:00
|
|
|
{ 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
|
|
|
|
{ 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
|
|
|
|
{ 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
|
2007-11-27 13:35:56 -07:00
|
|
|
{ 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
|
2008-10-13 13:39:50 -06:00
|
|
|
{ 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
|
2007-07-09 15:17:58 -06:00
|
|
|
{ 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
|
2009-01-06 09:21:01 -07:00
|
|
|
{ 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
|
|
|
|
{ 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
|
2008-04-28 15:44:43 -06:00
|
|
|
{ 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
|
2009-05-16 11:03:36 -06:00
|
|
|
{ 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
|
2007-07-09 15:17:58 -06:00
|
|
|
/* end marker */
|
|
|
|
{ 0, }
|
|
|
|
};
|
|
|
|
|
2008-08-05 10:17:04 -06:00
|
|
|
static u8 piix_cable_detect(ide_hwif_t *hwif)
|
2007-02-16 18:40:23 -07:00
|
|
|
{
|
2008-02-01 15:09:31 -07:00
|
|
|
struct pci_dev *pdev = to_pci_dev(hwif->dev);
|
2007-07-09 15:17:58 -06:00
|
|
|
const struct ich_laptop *lap = &ich_laptop[0];
|
2007-02-16 18:40:23 -07:00
|
|
|
u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
|
|
|
|
|
2007-07-09 15:17:58 -06:00
|
|
|
/* check for specials */
|
|
|
|
while (lap->device) {
|
|
|
|
if (lap->device == pdev->device &&
|
|
|
|
lap->subvendor == pdev->subsystem_vendor &&
|
|
|
|
lap->subdevice == pdev->subsystem_device) {
|
|
|
|
return ATA_CBL_PATA40_SHORT;
|
|
|
|
}
|
|
|
|
lap++;
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_read_config_byte(pdev, 0x54, ®54h);
|
2007-02-16 18:40:23 -07:00
|
|
|
|
2007-07-09 15:17:58 -06:00
|
|
|
return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
|
2007-02-16 18:40:23 -07:00
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/**
|
|
|
|
* init_hwif_piix - fill in the hwif for the PIIX
|
|
|
|
* @hwif: IDE interface
|
|
|
|
*
|
|
|
|
* Set up the ide_hwif_t for the PIIX interface according to the
|
|
|
|
* capabilities of the hardware.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void __devinit init_hwif_piix(ide_hwif_t *hwif)
|
|
|
|
{
|
|
|
|
if (!hwif->dma_base)
|
|
|
|
return;
|
|
|
|
|
2007-02-16 18:40:23 -07:00
|
|
|
if (no_piix_dma)
|
|
|
|
hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2008-04-26 14:25:14 -06:00
|
|
|
static const struct ide_port_ops piix_port_ops = {
|
|
|
|
.set_pio_mode = piix_set_pio_mode,
|
|
|
|
.set_dma_mode = piix_set_dma_mode,
|
|
|
|
.cable_detect = piix_cable_detect,
|
|
|
|
};
|
|
|
|
|
2008-10-13 13:39:42 -06:00
|
|
|
static const struct ide_port_ops ich_port_ops = {
|
|
|
|
.set_pio_mode = piix_set_pio_mode,
|
|
|
|
.set_dma_mode = piix_set_dma_mode,
|
|
|
|
.clear_irq = ich_clear_irq,
|
|
|
|
.cable_detect = piix_cable_detect,
|
|
|
|
};
|
|
|
|
|
2008-07-24 14:53:32 -06:00
|
|
|
#define DECLARE_PIIX_DEV(udma) \
|
2005-04-16 16:20:36 -06:00
|
|
|
{ \
|
2008-07-24 14:53:32 -06:00
|
|
|
.name = DRV_NAME, \
|
2005-04-16 16:20:36 -06:00
|
|
|
.init_hwif = init_hwif_piix, \
|
|
|
|
.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
|
2008-04-26 14:25:14 -06:00
|
|
|
.port_ops = &piix_port_ops, \
|
2007-07-19 17:11:59 -06:00
|
|
|
.pio_mask = ATA_PIO4, \
|
2007-10-18 16:30:07 -06:00
|
|
|
.swdma_mask = ATA_SWDMA2_ONLY, \
|
|
|
|
.mwdma_mask = ATA_MWDMA12_ONLY, \
|
2007-05-09 16:01:07 -06:00
|
|
|
.udma_mask = udma, \
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2008-07-24 14:53:32 -06:00
|
|
|
#define DECLARE_ICH_DEV(udma) \
|
2007-10-18 16:30:10 -06:00
|
|
|
{ \
|
2008-07-24 14:53:32 -06:00
|
|
|
.name = DRV_NAME, \
|
2007-10-18 16:30:10 -06:00
|
|
|
.init_chipset = init_chipset_ich, \
|
2008-10-13 13:39:42 -06:00
|
|
|
.init_hwif = init_hwif_piix, \
|
2007-10-18 16:30:10 -06:00
|
|
|
.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
|
2008-10-13 13:39:42 -06:00
|
|
|
.port_ops = &ich_port_ops, \
|
2007-10-18 16:30:10 -06:00
|
|
|
.pio_mask = ATA_PIO4, \
|
|
|
|
.swdma_mask = ATA_SWDMA2_ONLY, \
|
|
|
|
.mwdma_mask = ATA_MWDMA12_ONLY, \
|
|
|
|
.udma_mask = udma, \
|
|
|
|
}
|
|
|
|
|
2007-10-19 16:32:34 -06:00
|
|
|
static const struct ide_port_info piix_pci_info[] __devinitdata = {
|
2008-07-24 14:53:32 -06:00
|
|
|
/* 0: MPIIX */
|
2007-02-07 10:18:25 -07:00
|
|
|
{ /*
|
|
|
|
* MPIIX actually has only a single IDE channel mapped to
|
|
|
|
* the primary or secondary ports depending on the value
|
|
|
|
* of the bit 14 of the IDETIM register at offset 0x6c
|
|
|
|
*/
|
2008-07-24 14:53:32 -06:00
|
|
|
.name = DRV_NAME,
|
2007-02-07 10:18:25 -07:00
|
|
|
.enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
|
2009-03-24 16:22:52 -06:00
|
|
|
.host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA,
|
2007-07-19 17:11:59 -06:00
|
|
|
.pio_mask = ATA_PIO4,
|
2007-10-18 16:30:11 -06:00
|
|
|
/* This is a painful system best to let it self tune for now */
|
2005-04-16 16:20:36 -06:00
|
|
|
},
|
2008-07-24 14:53:32 -06:00
|
|
|
/* 1: PIIXa/PIIXb/PIIX3 */
|
|
|
|
DECLARE_PIIX_DEV(0x00), /* no udma */
|
|
|
|
/* 2: PIIX4 */
|
|
|
|
DECLARE_PIIX_DEV(ATA_UDMA2),
|
|
|
|
/* 3: ICH0 */
|
|
|
|
DECLARE_ICH_DEV(ATA_UDMA2),
|
|
|
|
/* 4: ICH */
|
|
|
|
DECLARE_ICH_DEV(ATA_UDMA4),
|
|
|
|
/* 5: PIIX4 */
|
|
|
|
DECLARE_PIIX_DEV(ATA_UDMA4),
|
|
|
|
/* 6: ICH[2-7]/ICH[2-3]M/C-ICH/ICH5-SATA/ESB2/ICH8M */
|
|
|
|
DECLARE_ICH_DEV(ATA_UDMA5),
|
2005-04-16 16:20:36 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* piix_init_one - called when a PIIX is found
|
|
|
|
* @dev: the piix device
|
|
|
|
* @id: the matching pci id
|
|
|
|
*
|
|
|
|
* Called when the PCI registration layer (or the IDE initialization)
|
|
|
|
* finds a device matching our IDE device tables.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|
|
|
{
|
2008-07-24 14:53:14 -06:00
|
|
|
return ide_pci_init_one(dev, &piix_pci_info[id->driver_data], NULL);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* piix_check_450nx - Check for problem 450NX setup
|
|
|
|
*
|
|
|
|
* Check for the present of 450NX errata #19 and errata #25. If
|
|
|
|
* they are found, disable use of DMA IDE
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void __devinit piix_check_450nx(void)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = NULL;
|
|
|
|
u16 cfg;
|
2006-10-01 00:27:28 -06:00
|
|
|
while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
/* Look for 450NX PXB. Check for problem configurations
|
|
|
|
A PCI quirk checks bit 6 already */
|
|
|
|
pci_read_config_word(pdev, 0x41, &cfg);
|
|
|
|
/* Only on the original revision: IDE DMA can hang */
|
2007-06-08 16:46:36 -06:00
|
|
|
if (pdev->revision == 0x00)
|
2005-04-16 16:20:36 -06:00
|
|
|
no_piix_dma = 1;
|
|
|
|
/* On all revisions below 5 PXB bus lock must be disabled for IDE */
|
2007-06-08 16:46:36 -06:00
|
|
|
else if (cfg & (1<<14) && pdev->revision < 5)
|
2005-04-16 16:20:36 -06:00
|
|
|
no_piix_dma = 2;
|
|
|
|
}
|
|
|
|
if(no_piix_dma)
|
2008-07-24 14:53:32 -06:00
|
|
|
printk(KERN_WARNING DRV_NAME ": 450NX errata present, disabling IDE DMA.\n");
|
2005-04-16 16:20:36 -06:00
|
|
|
if(no_piix_dma == 2)
|
2008-07-24 14:53:32 -06:00
|
|
|
printk(KERN_WARNING DRV_NAME ": A BIOS update may resolve this.\n");
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2007-10-16 14:29:56 -06:00
|
|
|
static const struct pci_device_id piix_pci_tbl[] = {
|
2008-07-24 14:53:32 -06:00
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0), 1 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1), 1 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), 0 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1), 1 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB), 2 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1), 3 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1), 2 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1), 4 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1), 5 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX), 2 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9), 6 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8), 6 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 6 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 6 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 6 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 6 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11), 6 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 6 },
|
2005-04-16 16:20:36 -06:00
|
|
|
#ifdef CONFIG_BLK_DEV_IDE_SATA
|
2008-07-24 14:53:32 -06:00
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1), 6 },
|
2005-04-16 16:20:36 -06:00
|
|
|
#endif
|
2008-07-24 14:53:32 -06:00
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2), 6 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19), 6 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21), 6 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1), 6 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18), 6 },
|
|
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6), 6 },
|
2005-04-16 16:20:36 -06:00
|
|
|
{ 0, },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
|
|
|
|
|
2008-10-13 13:39:41 -06:00
|
|
|
static struct pci_driver piix_pci_driver = {
|
2005-04-16 16:20:36 -06:00
|
|
|
.name = "PIIX_IDE",
|
|
|
|
.id_table = piix_pci_tbl,
|
|
|
|
.probe = piix_init_one,
|
2008-07-24 14:53:24 -06:00
|
|
|
.remove = ide_pci_remove,
|
2008-10-10 14:39:32 -06:00
|
|
|
.suspend = ide_pci_suspend,
|
|
|
|
.resume = ide_pci_resume,
|
2005-04-16 16:20:36 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static int __init piix_ide_init(void)
|
|
|
|
{
|
|
|
|
piix_check_450nx();
|
2008-10-13 13:39:41 -06:00
|
|
|
return ide_pci_register_driver(&piix_pci_driver);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2008-07-24 14:53:24 -06:00
|
|
|
static void __exit piix_ide_exit(void)
|
|
|
|
{
|
2008-10-13 13:39:41 -06:00
|
|
|
pci_unregister_driver(&piix_pci_driver);
|
2008-07-24 14:53:24 -06:00
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
module_init(piix_ide_init);
|
2008-07-24 14:53:24 -06:00
|
|
|
module_exit(piix_ide_exit);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
|
|
|
|
MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
|
|
|
|
MODULE_LICENSE("GPL");
|