blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
/*
|
|
|
|
|
* File: include/asm-blackfin/mach-bf533/bf533.h
|
|
|
|
|
* Based on:
|
|
|
|
|
* Author:
|
|
|
|
|
*
|
|
|
|
|
* Created:
|
|
|
|
|
* Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
|
|
|
|
|
*
|
|
|
|
|
* Modified:
|
|
|
|
|
* Copyright 2004-2006 Analog Devices Inc.
|
|
|
|
|
*
|
|
|
|
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
|
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
|
|
|
* (at your option) any later version.
|
|
|
|
|
*
|
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
|
*
|
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
|
* along with this program; if not, see the file COPYING, or write
|
|
|
|
|
* to the Free Software Foundation, Inc.,
|
|
|
|
|
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifndef __MACH_BF533_H__
|
|
|
|
|
#define __MACH_BF533_H__
|
|
|
|
|
|
|
|
|
|
#define SUPPORTED_REVID 2
|
|
|
|
|
|
|
|
|
|
#define OFFSET_(x) ((x) & 0x0000FFFF)
|
|
|
|
|
|
|
|
|
|
/*some misc defines*/
|
|
|
|
|
#define IMASK_IVG15 0x8000
|
|
|
|
|
#define IMASK_IVG14 0x4000
|
|
|
|
|
#define IMASK_IVG13 0x2000
|
|
|
|
|
#define IMASK_IVG12 0x1000
|
|
|
|
|
|
|
|
|
|
#define IMASK_IVG11 0x0800
|
|
|
|
|
#define IMASK_IVG10 0x0400
|
|
|
|
|
#define IMASK_IVG9 0x0200
|
|
|
|
|
#define IMASK_IVG8 0x0100
|
|
|
|
|
|
|
|
|
|
#define IMASK_IVG7 0x0080
|
|
|
|
|
#define IMASK_IVGTMR 0x0040
|
|
|
|
|
#define IMASK_IVGHW 0x0020
|
|
|
|
|
|
|
|
|
|
/***************************/
|
|
|
|
|
|
|
|
|
|
|
2007-10-10 09:55:26 -06:00
|
|
|
#define BFIN_DSUBBANKS 4
|
|
|
|
|
#define BFIN_DWAYS 2
|
|
|
|
|
#define BFIN_DLINES 64
|
|
|
|
|
#define BFIN_ISUBBANKS 4
|
|
|
|
|
#define BFIN_IWAYS 4
|
|
|
|
|
#define BFIN_ILINES 32
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
|
|
|
|
|
#define WAY0_L 0x1
|
|
|
|
|
#define WAY1_L 0x2
|
|
|
|
|
#define WAY01_L 0x3
|
|
|
|
|
#define WAY2_L 0x4
|
|
|
|
|
#define WAY02_L 0x5
|
|
|
|
|
#define WAY12_L 0x6
|
|
|
|
|
#define WAY012_L 0x7
|
|
|
|
|
|
|
|
|
|
#define WAY3_L 0x8
|
|
|
|
|
#define WAY03_L 0x9
|
|
|
|
|
#define WAY13_L 0xA
|
|
|
|
|
#define WAY013_L 0xB
|
|
|
|
|
|
|
|
|
|
#define WAY32_L 0xC
|
|
|
|
|
#define WAY320_L 0xD
|
|
|
|
|
#define WAY321_L 0xE
|
|
|
|
|
#define WAYALL_L 0xF
|
|
|
|
|
|
|
|
|
|
#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
|
|
|
|
|
|
|
|
|
|
/* IAR0 BIT FIELDS*/
|
|
|
|
|
#define RTC_ERROR_BIT 0x0FFFFFFF
|
|
|
|
|
#define UART_ERROR_BIT 0xF0FFFFFF
|
|
|
|
|
#define SPORT1_ERROR_BIT 0xFF0FFFFF
|
|
|
|
|
#define SPI_ERROR_BIT 0xFFF0FFFF
|
|
|
|
|
#define SPORT0_ERROR_BIT 0xFFFF0FFF
|
|
|
|
|
#define PPI_ERROR_BIT 0xFFFFF0FF
|
|
|
|
|
#define DMA_ERROR_BIT 0xFFFFFF0F
|
|
|
|
|
#define PLLWAKE_ERROR_BIT 0xFFFFFFFF
|
|
|
|
|
|
|
|
|
|
/* IAR1 BIT FIELDS*/
|
|
|
|
|
#define DMA7_UARTTX_BIT 0x0FFFFFFF
|
|
|
|
|
#define DMA6_UARTRX_BIT 0xF0FFFFFF
|
|
|
|
|
#define DMA5_SPI_BIT 0xFF0FFFFF
|
|
|
|
|
#define DMA4_SPORT1TX_BIT 0xFFF0FFFF
|
|
|
|
|
#define DMA3_SPORT1RX_BIT 0xFFFF0FFF
|
|
|
|
|
#define DMA2_SPORT0TX_BIT 0xFFFFF0FF
|
|
|
|
|
#define DMA1_SPORT0RX_BIT 0xFFFFFF0F
|
|
|
|
|
#define DMA0_PPI_BIT 0xFFFFFFFF
|
|
|
|
|
|
|
|
|
|
/* IAR2 BIT FIELDS*/
|
|
|
|
|
#define WDTIMER_BIT 0x0FFFFFFF
|
|
|
|
|
#define MEMDMA1_BIT 0xF0FFFFFF
|
|
|
|
|
#define MEMDMA0_BIT 0xFF0FFFFF
|
|
|
|
|
#define PFB_BIT 0xFFF0FFFF
|
|
|
|
|
#define PFA_BIT 0xFFFF0FFF
|
|
|
|
|
#define TIMER2_BIT 0xFFFFF0FF
|
|
|
|
|
#define TIMER1_BIT 0xFFFFFF0F
|
|
|
|
|
#define TIMER0_BIT 0xFFFFFFFF
|
|
|
|
|
|
|
|
|
|
/********************************* EBIU Settings ************************************/
|
|
|
|
|
#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
|
|
|
|
|
#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_C_AMBEN_ALL
|
|
|
|
|
#define V_AMBEN AMBEN_ALL
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_C_AMBEN
|
|
|
|
|
#define V_AMBEN 0x0
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_C_AMBEN_B0
|
|
|
|
|
#define V_AMBEN AMBEN_B0
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_C_AMBEN_B0_B1
|
|
|
|
|
#define V_AMBEN AMBEN_B0_B1
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_C_AMBEN_B0_B1_B2
|
|
|
|
|
#define V_AMBEN AMBEN_B0_B1_B2
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_C_AMCKEN
|
|
|
|
|
#define V_AMCKEN AMCKEN
|
|
|
|
|
#else
|
|
|
|
|
#define V_AMCKEN 0x0
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_C_CDPRIO
|
|
|
|
|
#define V_CDPRIO 0x100
|
|
|
|
|
#else
|
|
|
|
|
#define V_CDPRIO 0x0
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_BF533
|
|
|
|
|
#define CPU "BF533"
|
|
|
|
|
#define CPUID 0x027a5000
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_BF532
|
|
|
|
|
#define CPU "BF532"
|
|
|
|
|
#define CPUID 0x0275A000
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_BF531
|
|
|
|
|
#define CPU "BF531"
|
|
|
|
|
#define CPUID 0x027a5000
|
|
|
|
|
#endif
|
|
|
|
|
#ifndef CPU
|
|
|
|
|
#define CPU "UNKNOWN"
|
|
|
|
|
#define CPUID 0x0
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif /* __MACH_BF533_H__ */
|
