Blackfin arch: to do some consolidation of common code and common name spaces
now all BLKFIN should be BFIN, should be no functional changes. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Robin Getz
Bryan Wu
parent
a298049180
commit
3bebca2d20
31 changed files with 289 additions and 391 deletions
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@ -722,22 +722,22 @@ endchoice
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comment "Cache Support"
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config BLKFIN_CACHE
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config BFIN_ICACHE
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bool "Enable ICACHE"
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config BLKFIN_DCACHE
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config BFIN_DCACHE
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bool "Enable DCACHE"
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config BLKFIN_DCACHE_BANKA
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config BFIN_DCACHE_BANKA
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bool "Enable only 16k BankA DCACHE - BankB is SRAM"
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depends on BLKFIN_DCACHE && !BF531
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depends on BFIN_DCACHE && !BF531
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default n
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config BLKFIN_CACHE_LOCK
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bool "Enable Cache Locking"
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config BFIN_ICACHE_LOCK
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bool "Enable Instruction Cache Locking"
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choice
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prompt "Policy"
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depends on BLKFIN_DCACHE
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default BLKFIN_WB
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config BLKFIN_WB
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depends on BFIN_DCACHE
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default BFIN_WB
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config BFIN_WB
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bool "Write back"
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help
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Write Back Policy:
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@ -754,7 +754,7 @@ config BLKFIN_WB
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If you are unsure of the options and you want to be safe,
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then go with Write Through.
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config BLKFIN_WT
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config BFIN_WT
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bool "Write through"
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help
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Write Back Policy:
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@ -243,12 +243,12 @@ CONFIG_DMA_UNCACHED_1M=y
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#
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# Cache Support
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#
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CONFIG_BLKFIN_CACHE=y
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CONFIG_BLKFIN_DCACHE=y
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# CONFIG_BLKFIN_DCACHE_BANKA is not set
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# CONFIG_BLKFIN_CACHE_LOCK is not set
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# CONFIG_BLKFIN_WB is not set
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CONFIG_BLKFIN_WT=y
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CONFIG_BFIN_ICACHE=y
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CONFIG_BFIN_DCACHE=y
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# CONFIG_BFIN_DCACHE_BANKA is not set
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# CONFIG_BFIN_ICACHE_LOCK is not set
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# CONFIG_BFIN_WB is not set
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CONFIG_BFIN_WT=y
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CONFIG_L1_MAX_PIECE=16
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#
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@ -255,12 +255,12 @@ CONFIG_DMA_UNCACHED_1M=y
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#
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# Cache Support
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#
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CONFIG_BLKFIN_CACHE=y
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CONFIG_BLKFIN_DCACHE=y
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# CONFIG_BLKFIN_DCACHE_BANKA is not set
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# CONFIG_BLKFIN_CACHE_LOCK is not set
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# CONFIG_BLKFIN_WB is not set
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CONFIG_BLKFIN_WT=y
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CONFIG_BFIN_ICACHE=y
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CONFIG_BFIN_DCACHE=y
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# CONFIG_BFIN_DCACHE_BANKA is not set
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# CONFIG_BFIN_ICACHE_LOCK is not set
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# CONFIG_BFIN_WB is not set
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CONFIG_BFIN_WT=y
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CONFIG_L1_MAX_PIECE=16
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#
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@ -258,12 +258,12 @@ CONFIG_DMA_UNCACHED_1M=y
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#
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# Cache Support
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#
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CONFIG_BLKFIN_CACHE=y
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CONFIG_BLKFIN_DCACHE=y
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# CONFIG_BLKFIN_DCACHE_BANKA is not set
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# CONFIG_BLKFIN_CACHE_LOCK is not set
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# CONFIG_BLKFIN_WB is not set
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CONFIG_BLKFIN_WT=y
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CONFIG_BFIN_ICACHE=y
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CONFIG_BFIN_DCACHE=y
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# CONFIG_BFIN_DCACHE_BANKA is not set
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# CONFIG_BFIN_ICACHE_LOCK is not set
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# CONFIG_BFIN_WB is not set
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CONFIG_BFIN_WT=y
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CONFIG_L1_MAX_PIECE=16
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#
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@ -306,12 +306,12 @@ CONFIG_DMA_UNCACHED_1M=y
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#
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# Cache Support
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#
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CONFIG_BLKFIN_CACHE=y
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CONFIG_BLKFIN_DCACHE=y
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# CONFIG_BLKFIN_DCACHE_BANKA is not set
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# CONFIG_BLKFIN_CACHE_LOCK is not set
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# CONFIG_BLKFIN_WB is not set
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CONFIG_BLKFIN_WT=y
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CONFIG_BFIN_ICACHE=y
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CONFIG_BFIN_DCACHE=y
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# CONFIG_BFIN_DCACHE_BANKA is not set
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# CONFIG_BFIN_ICACHE_LOCK is not set
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# CONFIG_BFIN_WB is not set
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CONFIG_BFIN_WT=y
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CONFIG_L1_MAX_PIECE=16
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#
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@ -288,12 +288,12 @@ CONFIG_DMA_UNCACHED_1M=y
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#
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# Cache Support
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#
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CONFIG_BLKFIN_CACHE=y
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CONFIG_BLKFIN_DCACHE=y
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# CONFIG_BLKFIN_DCACHE_BANKA is not set
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# CONFIG_BLKFIN_CACHE_LOCK is not set
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# CONFIG_BLKFIN_WB is not set
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CONFIG_BLKFIN_WT=y
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CONFIG_BFIN_ICACHE=y
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CONFIG_BFIN_DCACHE=y
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# CONFIG_BFIN_DCACHE_BANKA is not set
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# CONFIG_BFIN_ICACHE_LOCK is not set
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# CONFIG_BFIN_WB is not set
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CONFIG_BFIN_WT=y
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CONFIG_L1_MAX_PIECE=16
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#
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@ -257,12 +257,12 @@ CONFIG_DMA_UNCACHED_1M=y
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#
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# Cache Support
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#
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CONFIG_BLKFIN_CACHE=y
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CONFIG_BLKFIN_DCACHE=y
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# CONFIG_BLKFIN_DCACHE_BANKA is not set
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# CONFIG_BLKFIN_CACHE_LOCK is not set
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CONFIG_BLKFIN_WB=y
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# CONFIG_BLKFIN_WT is not set
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CONFIG_BFIN_ICACHE=y
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CONFIG_BFIN_DCACHE=y
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# CONFIG_BFIN_DCACHE_BANKA is not set
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# CONFIG_BFIN_ICACHE_LOCK is not set
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CONFIG_BFIN_WB=y
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# CONFIG_BFIN_WT is not set
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CONFIG_L1_MAX_PIECE=16
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#
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@ -21,9 +21,10 @@
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#include <asm/cacheflush.h>
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#include <asm/cplbinit.h>
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#if defined(CONFIG_BLKFIN_CACHE)
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#if defined(CONFIG_BFIN_ICACHE)
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void bfin_icache_init(void)
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{
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unsigned long *table = icplb_table;
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@ -44,7 +45,7 @@ void bfin_icache_init(void)
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}
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#endif
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#if defined(CONFIG_BLKFIN_DCACHE)
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#if defined(CONFIG_BFIN_DCACHE)
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void bfin_dcache_init(void)
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{
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unsigned long *table = dcplb_table;
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@ -23,6 +23,7 @@
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#include <linux/module.h>
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#include <asm/cplbinit.h>
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u_long icplb_table[MAX_CPLBS+1];
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@ -56,7 +57,7 @@ struct s_cplb {
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struct cplb_tab switch_d;
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};
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#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
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#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
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static struct cplb_desc cplb_data[] = {
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{
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.start = 0,
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@ -230,7 +231,7 @@ static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_en
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cplb_data[i].psize,
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cplb_data[i].i_conf);
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} else {
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#if defined(CONFIG_BLKFIN_CACHE)
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#if defined(CONFIG_BFIN_ICACHE)
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if (ANOMALY_05000263 && i == SDRAM_KERN) {
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fill_cplbtab(t,
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cplb_data[i].start,
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@ -136,7 +136,7 @@ void cpu_idle(void)
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void machine_restart(char *__unused)
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{
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#if defined(CONFIG_BLKFIN_CACHE)
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#if defined(CONFIG_BFIN_ICACHE)
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bfin_write_IMEM_CONTROL(0x01);
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SSYNC();
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#endif
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@ -39,6 +39,7 @@
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#include <linux/cramfs_fs.h>
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#include <linux/romfs_fs.h>
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#include <asm/cplb.h>
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#include <asm/cacheflush.h>
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#include <asm/blackfin.h>
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#include <asm/cplbinit.h>
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@ -66,21 +67,21 @@ char __initdata command_line[COMMAND_LINE_SIZE];
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void __init bf53x_cache_init(void)
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{
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#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
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#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
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generate_cpl_tables();
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#endif
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#ifdef CONFIG_BLKFIN_CACHE
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#ifdef CONFIG_BFIN_ICACHE
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bfin_icache_init();
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printk(KERN_INFO "Instruction Cache Enabled\n");
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#endif
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#ifdef CONFIG_BLKFIN_DCACHE
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#ifdef CONFIG_BFIN_DCACHE
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bfin_dcache_init();
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printk(KERN_INFO "Data Cache Enabled"
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# if defined CONFIG_BLKFIN_WB
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# if defined CONFIG_BFIN_WB
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" (write-back)"
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# elif defined CONFIG_BLKFIN_WT
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# elif defined CONFIG_BFIN_WT
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" (write-through)"
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# endif
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"\n");
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@ -262,7 +263,7 @@ void __init setup_arch(char **cmdline_p)
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&& ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
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mtd_size =
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PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
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# if (defined(CONFIG_BLKFIN_CACHE) && ANOMALY_05000263)
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# if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
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/* Due to a Hardware Anomaly we need to limit the size of usable
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* instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
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* 05000263 - Hardware loop corrupted when taking an ICPLB exception
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@ -291,7 +292,7 @@ void __init setup_arch(char **cmdline_p)
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_ebss = memory_mtd_start; /* define _ebss for compatible */
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#endif /* CONFIG_MTD_UCLINUX */
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#if (defined(CONFIG_BLKFIN_CACHE) && ANOMALY_05000263)
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#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
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/* Due to a Hardware Anomaly we need to limit the size of usable
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* instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
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* 05000263 - Hardware loop corrupted when taking an ICPLB exception
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@ -535,9 +536,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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seq_printf(m, "I-CACHE:\tOFF\n");
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if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE))
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seq_printf(m, "D-CACHE:\tON"
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#if defined CONFIG_BLKFIN_WB
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#if defined CONFIG_BFIN_WB
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" (write-back)"
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#elif defined CONFIG_BLKFIN_WT
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#elif defined CONFIG_BFIN_WT
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" (write-through)"
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#endif
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"\n");
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@ -566,15 +567,15 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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}
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seq_printf(m, "I-CACHE Size:\t%dKB\n", BLKFIN_ICACHESIZE / 1024);
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seq_printf(m, "I-CACHE Size:\t%dKB\n", BFIN_ICACHESIZE / 1024);
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seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size);
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seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n",
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BLKFIN_ISUBBANKS, BLKFIN_IWAYS, BLKFIN_ILINES);
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BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
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seq_printf(m,
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"D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
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dsup_banks, BLKFIN_DSUBBANKS, BLKFIN_DWAYS,
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BLKFIN_DLINES);
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#ifdef CONFIG_BLKFIN_CACHE_LOCK
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dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
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BFIN_DLINES);
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#ifdef CONFIG_BFIN_ICACHE_LOCK
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switch (read_iloc()) {
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case WAY0_L:
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seq_printf(m, "Way0 Locked-Down\n");
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@ -53,3 +53,8 @@
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# endif
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#endif /* CONFIG_BFIN_KERNEL_CLOCK */
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#if (CONFIG_MEM_SIZE % 4)
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#error "SDRAM mem size must be multible of 4MB"
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#endif
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@ -39,7 +39,7 @@
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.text
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#if ANOMALY_05000125
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#if defined(CONFIG_BLKFIN_CACHE)
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#if defined(CONFIG_BFIN_ICACHE)
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ENTRY(_bfin_write_IMEM_CONTROL)
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/* Enable Instruction Cache */
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@ -58,10 +58,10 @@ ENTRY(_bfin_write_IMEM_CONTROL)
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ENDPROC(_bfin_write_IMEM_CONTROL)
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#endif
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#if defined(CONFIG_BLKFIN_DCACHE)
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#if defined(CONFIG_BFIN_DCACHE)
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ENTRY(_bfin_write_DMEM_CONTROL)
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P0.l = (DMEM_CONTROL & 0xFFFF);
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P0.h = (DMEM_CONTROL >> 16);
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P0.l = LO(DMEM_CONTROL);
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P0.h = HI(DMEM_CONTROL);
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CLI R1;
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SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
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@ -69,14 +69,14 @@ ENTRY(__cplb_hdr)
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.Lis_icplb_miss:
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#if defined(CONFIG_BLKFIN_CACHE) || defined(CONFIG_BLKFIN_DCACHE)
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# if defined(CONFIG_BLKFIN_CACHE) && !defined(CONFIG_BLKFIN_DCACHE)
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#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
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# if defined(CONFIG_BFIN_ICACHE) && !defined(CONFIG_BFIN_DCACHE)
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R1 = CPLB_ENABLE_ICACHE;
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# endif
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# if !defined(CONFIG_BLKFIN_CACHE) && defined(CONFIG_BLKFIN_DCACHE)
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# if !defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
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R1 = CPLB_ENABLE_DCACHE;
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# endif
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# if defined(CONFIG_BLKFIN_CACHE) && defined(CONFIG_BLKFIN_DCACHE)
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# if defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
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R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
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# endif
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#else
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@ -565,7 +565,7 @@ ENTRY(_cplb_mgr)
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* cost of first-write exceptions to mark the page as dirty.
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*/
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#ifdef CONFIG_BLKFIN_WT
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#ifdef CONFIG_BFIN_WT
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BITSET(R6, 14); /* Set WT*/
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#endif
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@ -33,7 +33,7 @@
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.text
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#ifdef CONFIG_BLKFIN_CACHE_LOCK
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#ifdef CONFIG_BFIN_ICACHE_LOCK
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/* When you come here, it is assumed that
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* R0 - Which way to be locked
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@ -189,7 +189,7 @@ ENTRY(_cache_lock)
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RTS;
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ENDPROC(_cache_lock)
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#endif /* BLKFIN_CACHE_LOCK */
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#endif /* BFIN_ICACHE_LOCK */
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/* Return the ILOC bits of IMEM_CONTROL
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*/
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@ -48,9 +48,9 @@ extern void blackfin_dflush_page(void *);
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static inline void flush_icache_range(unsigned start, unsigned end)
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{
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#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_CACHE)
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#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE)
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# if defined(CONFIG_BLKFIN_WT)
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# if defined(CONFIG_BFIN_WT)
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blackfin_icache_flush_range((start), (end));
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# else
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blackfin_icache_dcache_flush_range((start), (end));
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@ -58,10 +58,10 @@ static inline void flush_icache_range(unsigned start, unsigned end)
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#else
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# if defined(CONFIG_BLKFIN_CACHE)
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# if defined(CONFIG_BFIN_ICACHE)
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blackfin_icache_flush_range((start), (end));
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# endif
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# if defined(CONFIG_BLKFIN_DCACHE)
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# if defined(CONFIG_BFIN_DCACHE)
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blackfin_dcache_flush_range((start), (end));
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# endif
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@ -74,12 +74,12 @@ do { memcpy(dst, src, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
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#if defined(CONFIG_BLKFIN_DCACHE)
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#if defined(CONFIG_BFIN_DCACHE)
|
||||
# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
|
||||
#else
|
||||
# define invalidate_dcache_range(start,end) do { } while (0)
|
||||
#endif
|
||||
#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_WB)
|
||||
#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB)
|
||||
# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
|
||||
# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
|
||||
#else
|
||||
|
|
@ -87,4 +87,4 @@ do { memcpy(dst, src, len); \
|
|||
# define flush_dcache_page(page) do { } while (0)
|
||||
#endif
|
||||
|
||||
#endif /* _BLACKFIN_CACHEFLUSH_H */
|
||||
#endif /* _BLACKFIN_ICACHEFLUSH_H */
|
||||
|
|
|
|||
|
|
@ -1,18 +1,93 @@
|
|||
/************************************************************************
|
||||
/*
|
||||
* File: include/asm-blackfin/cplb.h
|
||||
* Based on: include/asm-blackfin/mach-bf537/bf537.h
|
||||
* Author: Robin Getz <rgetz@blackfin.uclinux.org>
|
||||
*
|
||||
* cplb.h
|
||||
* Created: 2000
|
||||
* Description: Common CPLB definitions for CPLB init
|
||||
*
|
||||
* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
|
||||
* Modified:
|
||||
* Copyright 2004-2007 Analog Devices Inc.
|
||||
*
|
||||
************************************************************************/
|
||||
|
||||
/* Defines necessary for cplb initialisation routines. */
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _CPLB_H
|
||||
#define _CPLB_H
|
||||
|
||||
# include <asm/blackfin.h>
|
||||
|
||||
#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
|
||||
#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
|
||||
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
|
||||
|
||||
/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
|
||||
|
||||
#if ANOMALY_05000158
|
||||
#define ANOMALY_05000158_WORKAROUND 0x200
|
||||
#else
|
||||
#define ANOMALY_05000158_WORKAROUND 0x0
|
||||
#endif
|
||||
|
||||
#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
|
||||
|
||||
#ifdef CONFIG_BFIN_WB /*Write Back Policy */
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
|
||||
#else /*Write Through */
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
|
||||
#endif
|
||||
|
||||
#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
|
||||
#define SDRAM_DNON_CHBL (CPLB_COMMON)
|
||||
#define SDRAM_EBIU (CPLB_COMMON)
|
||||
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
|
||||
|
||||
#define SIZE_1K 0x00000400 /* 1K */
|
||||
#define SIZE_4K 0x00001000 /* 4K */
|
||||
#define SIZE_1M 0x00100000 /* 1M */
|
||||
#define SIZE_4M 0x00400000 /* 4M */
|
||||
|
||||
#define MAX_CPLBS (16 * 2)
|
||||
|
||||
/*
|
||||
* Number of required data CPLB switchtable entries
|
||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Data Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
* 1 for ASYNC Memory
|
||||
*/
|
||||
|
||||
|
||||
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
|
||||
|
||||
/*
|
||||
* Number of required instruction CPLB switchtable entries
|
||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Instruction Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
*/
|
||||
|
||||
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
|
||||
|
||||
|
||||
#define CPLB_ENABLE_ICACHE_P 0
|
||||
#define CPLB_ENABLE_DCACHE_P 1
|
||||
#define CPLB_ENABLE_DCACHE2_P 2
|
||||
|
|
@ -39,8 +114,6 @@
|
|||
#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
|
||||
#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
|
||||
|
||||
#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
|
||||
|
||||
#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
|
||||
#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
|
||||
#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
|
||||
|
|
|
|||
|
|
@ -52,12 +52,12 @@
|
|||
/***************************/
|
||||
|
||||
|
||||
#define BLKFIN_DSUBBANKS 4
|
||||
#define BLKFIN_DWAYS 2
|
||||
#define BLKFIN_DLINES 64
|
||||
#define BLKFIN_ISUBBANKS 4
|
||||
#define BLKFIN_IWAYS 4
|
||||
#define BLKFIN_ILINES 32
|
||||
#define BFIN_DSUBBANKS 4
|
||||
#define BFIN_DWAYS 2
|
||||
#define BFIN_DLINES 64
|
||||
#define BFIN_ISUBBANKS 4
|
||||
#define BFIN_IWAYS 4
|
||||
#define BFIN_ILINES 32
|
||||
|
||||
#define WAY0_L 0x1
|
||||
#define WAY1_L 0x2
|
||||
|
|
@ -167,10 +167,10 @@
|
|||
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
|
||||
|
||||
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
|
||||
/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
|
||||
|
||||
#define ANOMALY_05000158_WORKAROUND 0x200
|
||||
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
|
||||
#ifdef CONFIG_BFIN_WB /*Write Back Policy */
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
|
||||
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
|
||||
#else /*Write Through */
|
||||
|
|
|
|||
|
|
@ -51,10 +51,10 @@
|
|||
|
||||
/* Level 1 Memory */
|
||||
|
||||
#ifdef CONFIG_BLKFIN_CACHE
|
||||
#define BLKFIN_ICACHESIZE (16*1024)
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define BFIN_ICACHESIZE (16*1024)
|
||||
#else
|
||||
#define BLKFIN_ICACHESIZE (0*1024)
|
||||
#define BFIN_ICACHESIZE (0*1024)
|
||||
#endif
|
||||
|
||||
/* Memory Map for ADSP-BF533 processors */
|
||||
|
|
@ -64,35 +64,35 @@
|
|||
#define L1_DATA_A_START 0xFF800000
|
||||
#define L1_DATA_B_START 0xFF900000
|
||||
|
||||
#ifdef CONFIG_BLKFIN_CACHE
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define L1_CODE_LENGTH (0x14000 - 0x4000)
|
||||
#else
|
||||
#define L1_CODE_LENGTH 0x14000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE_BANKA
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (16*1024)
|
||||
#define BLKFIN_DSUPBANKS 1
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BLKFIN_DCACHESIZE (32*1024)
|
||||
#define BLKFIN_DSUPBANKS 2
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (0*1024)
|
||||
#define BLKFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BLKFIN_DCACHE*/
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
#endif
|
||||
|
||||
/* Memory Map for ADSP-BF532 processors */
|
||||
|
|
@ -102,36 +102,36 @@
|
|||
#define L1_DATA_A_START 0xFF804000
|
||||
#define L1_DATA_B_START 0xFF904000
|
||||
|
||||
#ifdef CONFIG_BLKFIN_CACHE
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define L1_CODE_LENGTH (0xC000 - 0x4000)
|
||||
#else
|
||||
#define L1_CODE_LENGTH 0xC000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE_BANKA
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x4000
|
||||
#define BLKFIN_DCACHESIZE (16*1024)
|
||||
#define BLKFIN_DSUPBANKS 1
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
|
||||
#define BLKFIN_DCACHESIZE (32*1024)
|
||||
#define BLKFIN_DSUPBANKS 2
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x4000
|
||||
#define L1_DATA_B_LENGTH 0x4000
|
||||
#define BLKFIN_DCACHESIZE (0*1024)
|
||||
#define BLKFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BLKFIN_DCACHE*/
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
#endif
|
||||
|
||||
/* Memory Map for ADSP-BF531 processors */
|
||||
|
|
@ -144,16 +144,16 @@
|
|||
#define L1_DATA_B_LENGTH 0x0000
|
||||
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
|
||||
#define BLKFIN_DCACHESIZE (16*1024)
|
||||
#define BLKFIN_DSUPBANKS 1
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x4000
|
||||
#define BLKFIN_DCACHESIZE (0*1024)
|
||||
#define BLKFIN_DSUPBANKS 0
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -133,6 +133,7 @@
|
|||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000125 (0)
|
||||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000198 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
|
|
|
|||
|
|
@ -62,12 +62,12 @@
|
|||
/***************************/
|
||||
|
||||
|
||||
#define BLKFIN_DSUBBANKS 4
|
||||
#define BLKFIN_DWAYS 2
|
||||
#define BLKFIN_DLINES 64
|
||||
#define BLKFIN_ISUBBANKS 4
|
||||
#define BLKFIN_IWAYS 4
|
||||
#define BLKFIN_ILINES 32
|
||||
#define BFIN_DSUBBANKS 4
|
||||
#define BFIN_DWAYS 2
|
||||
#define BFIN_DLINES 64
|
||||
#define BFIN_ISUBBANKS 4
|
||||
#define BFIN_IWAYS 4
|
||||
#define BFIN_ILINES 32
|
||||
|
||||
#define WAY0_L 0x1
|
||||
#define WAY1_L 0x2
|
||||
|
|
@ -138,59 +138,4 @@
|
|||
#define CPUID 0x0
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_SIZE % 4)
|
||||
#error "SDRAM mem size must be multible of 4MB"
|
||||
#endif
|
||||
|
||||
#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
|
||||
#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
|
||||
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
|
||||
|
||||
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
|
||||
|
||||
#define ANOMALY_05000158_WORKAROUND 0x200
|
||||
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
|
||||
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
|
||||
#else /*Write Through */
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
|
||||
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
|
||||
#endif
|
||||
|
||||
|
||||
#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
|
||||
#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
|
||||
#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
|
||||
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
|
||||
|
||||
#define SIZE_1K 0x00000400 /* 1K */
|
||||
#define SIZE_4K 0x00001000 /* 4K */
|
||||
#define SIZE_1M 0x00100000 /* 1M */
|
||||
#define SIZE_4M 0x00400000 /* 4M */
|
||||
|
||||
#define MAX_CPLBS (16 * 2)
|
||||
|
||||
/*
|
||||
* Number of required data CPLB switchtable entries
|
||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Data Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
* 1 for ASYNC Memory
|
||||
*/
|
||||
|
||||
|
||||
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
|
||||
|
||||
/*
|
||||
* Number of required instruction CPLB switchtable entries
|
||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Instruction Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
*/
|
||||
|
||||
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
|
||||
|
||||
#endif /* __MACH_BF537_H__ */
|
||||
|
|
|
|||
|
|
@ -52,10 +52,10 @@
|
|||
|
||||
/* Memory Map for ADSP-BF537 processors */
|
||||
|
||||
#ifdef CONFIG_BLKFIN_CACHE
|
||||
#define BLKFIN_ICACHESIZE (16*1024)
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define BFIN_ICACHESIZE (16*1024)
|
||||
#else
|
||||
#define BLKFIN_ICACHESIZE (0*1024)
|
||||
#define BFIN_ICACHESIZE (0*1024)
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -66,29 +66,29 @@
|
|||
|
||||
#define L1_CODE_LENGTH 0xC000
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE_BANKA
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (16*1024)
|
||||
#define BLKFIN_DSUPBANKS 1
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BLKFIN_DCACHESIZE (32*1024)
|
||||
#define BLKFIN_DSUPBANKS 2
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (0*1024)
|
||||
#define BLKFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BLKFIN_DCACHE*/
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
|
||||
#endif /*CONFIG_BF537*/
|
||||
|
||||
|
|
@ -102,30 +102,30 @@
|
|||
#define L1_CODE_LENGTH 0xC000
|
||||
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE_BANKA
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x4000
|
||||
#define BLKFIN_DCACHESIZE (16*1024)
|
||||
#define BLKFIN_DSUPBANKS 1
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
|
||||
#define BLKFIN_DCACHESIZE (32*1024)
|
||||
#define BLKFIN_DSUPBANKS 2
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x4000
|
||||
#define L1_DATA_B_LENGTH 0x4000
|
||||
#define BLKFIN_DCACHESIZE (0*1024)
|
||||
#define BLKFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BLKFIN_DCACHE*/
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -138,30 +138,30 @@
|
|||
|
||||
#define L1_CODE_LENGTH 0xC000
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE_BANKA
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (16*1024)
|
||||
#define BLKFIN_DSUPBANKS 1
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BLKFIN_DCACHESIZE (32*1024)
|
||||
#define BLKFIN_DSUPBANKS 2
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (0*1024)
|
||||
#define BLKFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BLKFIN_DCACHE*/
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -52,12 +52,12 @@
|
|||
/***************************/
|
||||
|
||||
|
||||
#define BLKFIN_DSUBBANKS 4
|
||||
#define BLKFIN_DWAYS 2
|
||||
#define BLKFIN_DLINES 64
|
||||
#define BLKFIN_ISUBBANKS 4
|
||||
#define BLKFIN_IWAYS 4
|
||||
#define BLKFIN_ILINES 32
|
||||
#define BFIN_DSUBBANKS 4
|
||||
#define BFIN_DWAYS 2
|
||||
#define BFIN_DLINES 64
|
||||
#define BFIN_ISUBBANKS 4
|
||||
#define BFIN_IWAYS 4
|
||||
#define BFIN_ILINES 32
|
||||
|
||||
#define WAY0_L 0x1
|
||||
#define WAY1_L 0x2
|
||||
|
|
@ -126,59 +126,4 @@
|
|||
#define CPUID 0x0
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_SIZE % 4)
|
||||
#error "SDRAM mem size must be multible of 4MB"
|
||||
#endif
|
||||
|
||||
#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
|
||||
#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
|
||||
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
|
||||
|
||||
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
|
||||
|
||||
#define ANOMALY_05000158_WORKAROUND 0x200
|
||||
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
|
||||
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
|
||||
#else /*Write Through */
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
|
||||
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
|
||||
#endif
|
||||
|
||||
|
||||
#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
|
||||
#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
|
||||
#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
|
||||
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
|
||||
|
||||
#define SIZE_1K 0x00000400 /* 1K */
|
||||
#define SIZE_4K 0x00001000 /* 4K */
|
||||
#define SIZE_1M 0x00100000 /* 1M */
|
||||
#define SIZE_4M 0x00400000 /* 4M */
|
||||
|
||||
#define MAX_CPLBS (16 * 2)
|
||||
|
||||
/*
|
||||
* Number of required data CPLB switchtable entries
|
||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Data Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
* 1 for ASYNC Memory
|
||||
*/
|
||||
|
||||
|
||||
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
|
||||
|
||||
/*
|
||||
* Number of required instruction CPLB switchtable entries
|
||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Instruction Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
*/
|
||||
|
||||
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
|
||||
|
||||
#endif /* __MACH_BF48_H__ */
|
||||
|
|
|
|||
|
|
@ -51,10 +51,10 @@
|
|||
/* Level 1 Memory */
|
||||
|
||||
/* Memory Map for ADSP-BF548 processors */
|
||||
#ifdef CONFIG_BLKFIN_ICACHE
|
||||
#define BLKFIN_ICACHESIZE (16*1024)
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define BFIN_ICACHESIZE (16*1024)
|
||||
#else
|
||||
#define BLKFIN_ICACHESIZE (0*1024)
|
||||
#define BFIN_ICACHESIZE (0*1024)
|
||||
#endif
|
||||
|
||||
#define L1_CODE_START 0xFFA00000
|
||||
|
|
@ -63,29 +63,29 @@
|
|||
|
||||
#define L1_CODE_LENGTH 0xC000
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE_BANKA
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (16*1024)
|
||||
#define BLKFIN_DSUPBANKS 1
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BLKFIN_DCACHESIZE (32*1024)
|
||||
#define BLKFIN_DSUPBANKS 2
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (0*1024)
|
||||
#define BLKFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BLKFIN_DCACHE*/
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
|
||||
/* Scratch Pad Memory */
|
||||
|
||||
|
|
|
|||
|
|
@ -73,13 +73,13 @@
|
|||
*/
|
||||
|
||||
|
||||
#define BLKFIN_ISUBBANKS 4
|
||||
#define BLKFIN_IWAYS 4
|
||||
#define BLKFIN_ILINES 32
|
||||
#define BFIN_ISUBBANKS 4
|
||||
#define BFIN_IWAYS 4
|
||||
#define BFIN_ILINES 32
|
||||
|
||||
#define BLKFIN_DSUBBANKS 4
|
||||
#define BLKFIN_DWAYS 2
|
||||
#define BLKFIN_DLINES 64
|
||||
#define BFIN_DSUBBANKS 4
|
||||
#define BFIN_DWAYS 2
|
||||
#define BFIN_DLINES 64
|
||||
|
||||
#define WAY0_L 0x1
|
||||
#define WAY1_L 0x2
|
||||
|
|
@ -239,83 +239,4 @@
|
|||
#define CPUID 0x0
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_SIZE % 4)
|
||||
#error "SDRAM memory size must be a multiple of 4MB!"
|
||||
#endif
|
||||
#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
|
||||
#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
|
||||
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
|
||||
|
||||
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
|
||||
|
||||
#define ANOMALY_05000158_WORKAROUND 0x200
|
||||
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
|
||||
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
|
||||
#else /*Write Through */
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \
|
||||
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
|
||||
#endif
|
||||
|
||||
|
||||
#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
|
||||
#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
|
||||
#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
|
||||
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
|
||||
|
||||
#define L2_MEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
|
||||
|
||||
#define SIZE_1K 0x00000400 /* 1K */
|
||||
#define SIZE_4K 0x00001000 /* 4K */
|
||||
#define SIZE_1M 0x00100000 /* 1M */
|
||||
#define SIZE_4M 0x00400000 /* 4M */
|
||||
|
||||
#define MAX_CPLBS (16 * 2)
|
||||
|
||||
/*
|
||||
* Number of required data CPLB switchtable entries
|
||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Data Memory
|
||||
* 1 for L2 Data Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
* 64 for ASYNC Memory
|
||||
*/
|
||||
|
||||
|
||||
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 + 64) * 2)
|
||||
|
||||
/*
|
||||
* Number of required instruction CPLB switchtable entries
|
||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Instruction Memory
|
||||
* 1 for L2 Instruction Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
*/
|
||||
|
||||
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
|
||||
|
||||
#if 0 /* comment by mhfan */
|
||||
/* Event Vector Table Address */
|
||||
#define EVT_EMULATION_ADDR 0xffe02000
|
||||
#define EVT_RESET_ADDR 0xffe02004
|
||||
#define EVT_NMI_ADDR 0xffe02008
|
||||
#define EVT_EXCEPTION_ADDR 0xffe0200c
|
||||
#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
|
||||
#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
|
||||
#define EVT_TIMER_ADDR 0xffe02018
|
||||
#define EVT_IVG7_ADDR 0xffe0201c
|
||||
#define EVT_IVG8_ADDR 0xffe02020
|
||||
#define EVT_IVG9_ADDR 0xffe02024
|
||||
#define EVT_IVG10_ADDR 0xffe02028
|
||||
#define EVT_IVG11_ADDR 0xffe0202c
|
||||
#define EVT_IVG12_ADDR 0xffe02030
|
||||
#define EVT_IVG13_ADDR 0xffe02034
|
||||
#define EVT_IVG14_ADDR 0xffe02038
|
||||
#define EVT_IVG15_ADDR 0xffe0203c
|
||||
#define EVT_OVERRIDE_ADDR 0xffe02100
|
||||
#endif /* comment by mhfan */
|
||||
|
||||
#endif /* __MACH_BF561_H__ */
|
||||
|
|
|
|||
|
|
@ -21,10 +21,10 @@
|
|||
|
||||
/* Level 1 Memory */
|
||||
|
||||
#ifdef CONFIG_BLKFIN_CACHE
|
||||
#define BLKFIN_ICACHESIZE (16*1024)
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define BFIN_ICACHESIZE (16*1024)
|
||||
#else
|
||||
#define BLKFIN_ICACHESIZE (0*1024)
|
||||
#define BFIN_ICACHESIZE (0*1024)
|
||||
#endif
|
||||
|
||||
/* Memory Map for ADSP-BF561 processors */
|
||||
|
|
@ -36,29 +36,29 @@
|
|||
|
||||
#define L1_CODE_LENGTH 0x4000
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE_BANKA
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (16*1024)
|
||||
#define BLKFIN_DSUPBANKS 1
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BLKFIN_DCACHESIZE (32*1024)
|
||||
#define BLKFIN_DSUPBANKS 2
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (0*1024)
|
||||
#define BLKFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BLKFIN_DCACHE*/
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
#endif
|
||||
|
||||
/* Level 2 Memory */
|
||||
|
|
|
|||
|
|
@ -27,7 +27,8 @@
|
|||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _BFIN_CLOCKS_H
|
||||
#define _BFIN_CLOCKS_H
|
||||
|
||||
#ifdef CONFIG_CCLK_DIV_1
|
||||
# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
|
||||
|
|
@ -66,3 +67,4 @@
|
|||
# define CONFIG_VCO_MULT 0
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -639,6 +639,7 @@
|
|||
#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
|
||||
* allowed (user mode)
|
||||
*/
|
||||
|
||||
#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
|
||||
#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
|
||||
#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
|
||||
|
|
@ -671,6 +672,8 @@
|
|||
*/
|
||||
#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
|
||||
|
||||
#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
|
||||
|
||||
/* TBUFCTL Masks */
|
||||
#define TBUFPWR 0x0001
|
||||
#define TBUFEN 0x0002
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
#include <asm-generic/4level-fixup.h>
|
||||
|
||||
#include <asm/page.h>
|
||||
#include <asm/cplb.h>
|
||||
#include <asm/mach-common/def_LPBlackfin.h>
|
||||
|
||||
typedef pte_t *pte_addr_t;
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ extern unsigned long irq_flags;
|
|||
); \
|
||||
} while (0)
|
||||
|
||||
#if ANOMALY_05000244 && defined(CONFIG_BLKFIN_CACHE)
|
||||
#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
|
||||
# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
|
||||
#else
|
||||
# define NOP_PAD_ANOMALY_05000244
|
||||
|
|
|
|||
Loading…
Reference in a new issue