2006-08-29 16:12:40 -06:00
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/*
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* pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
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* (C) 2005 Red Hat Inc
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2008-10-27 09:09:10 -06:00
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* Alan Cox <alan@lxorguk.ukuu.org.uk>
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2010-02-13 06:35:53 -07:00
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* (C) 2007,2009,2010 Bartlomiej Zolnierkiewicz
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2006-08-29 16:12:40 -06:00
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*
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* Based in part on linux/drivers/ide/pci/pdc202xx_old.c
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*
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* First cut with LBA48/ATAPI
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*
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* TODO:
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2007-09-26 08:23:17 -06:00
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* Channel interlock/reset on both required ?
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2006-08-29 16:12:40 -06:00
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*/
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2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_pdc202xx_old"
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2007-09-26 08:23:17 -06:00
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#define DRV_VERSION "0.4.3"
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2006-08-29 16:12:40 -06:00
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2007-03-09 05:24:15 -07:00
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static int pdc2026x_cable_detect(struct ata_port *ap)
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2006-08-29 16:12:40 -06:00
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u16 cis;
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2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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pci_read_config_word(pdev, 0x50, &cis);
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if (cis & (1 << (10 + ap->port_no)))
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2007-07-03 08:15:13 -06:00
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return ATA_CBL_PATA40;
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return ATA_CBL_PATA80;
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2006-08-29 16:12:40 -06:00
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}
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2010-02-13 15:43:17 -07:00
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static void pdc202xx_exec_command(struct ata_port *ap,
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2010-02-13 06:35:53 -07:00
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const struct ata_taskfile *tf)
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{
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DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
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iowrite8(tf->command, ap->ioaddr.command_addr);
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ndelay(400);
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}
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2010-10-08 08:57:45 -06:00
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static bool pdc202xx_irq_check(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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unsigned long master = pci_resource_start(pdev, 4);
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u8 sc1d = inb(master + 0x1d);
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if (ap->port_no) {
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/*
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* bit 7: error, bit 6: interrupting,
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* bit 5: FIFO full, bit 4: FIFO empty
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*/
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return sc1d & 0x40;
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} else {
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/*
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* bit 3: error, bit 2: interrupting,
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* bit 1: FIFO full, bit 0: FIFO empty
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*/
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return sc1d & 0x04;
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}
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}
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2006-08-29 16:12:40 -06:00
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/**
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2006-11-03 06:18:06 -07:00
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* pdc202xx_configure_piomode - set chip PIO timing
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2006-08-29 16:12:40 -06:00
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* @ap: ATA interface
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* @adev: ATA device
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* @pio: PIO mode
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* so a configure_dmamode call will undo any work we do here and vice
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* versa
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*/
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2006-08-30 22:03:49 -06:00
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2006-11-03 06:18:06 -07:00
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static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
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2006-08-29 16:12:40 -06:00
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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2007-03-03 20:48:08 -07:00
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int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
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2006-08-29 16:12:40 -06:00
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static u16 pio_timing[5] = {
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0x0913, 0x050C , 0x0308, 0x0206, 0x0104
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};
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u8 r_ap, r_bp;
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pci_read_config_byte(pdev, port, &r_ap);
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pci_read_config_byte(pdev, port + 1, &r_bp);
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r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
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2007-03-03 20:48:08 -07:00
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r_bp &= ~0x1F;
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2006-08-29 16:12:40 -06:00
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r_ap |= (pio_timing[pio] >> 8);
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r_bp |= (pio_timing[pio] & 0xFF);
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2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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if (ata_pio_need_iordy(adev))
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r_ap |= 0x20; /* IORDY enable */
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if (adev->class == ATA_DEV_ATA)
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r_ap |= 0x10; /* FIFO enable */
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pci_write_config_byte(pdev, port, r_ap);
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pci_write_config_byte(pdev, port + 1, r_bp);
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}
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/**
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2006-11-03 06:18:06 -07:00
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* pdc202xx_set_piomode - set initial PIO mode data
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2006-08-29 16:12:40 -06:00
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* but we want to set the PIO timing by default.
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*/
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2006-08-30 22:03:49 -06:00
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2006-11-03 06:18:06 -07:00
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static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
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2006-08-29 16:12:40 -06:00
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{
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2006-11-03 06:18:06 -07:00
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pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
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2006-08-29 16:12:40 -06:00
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}
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/**
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2006-11-03 06:18:06 -07:00
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* pdc202xx_configure_dmamode - set DMA mode in chip
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2006-08-29 16:12:40 -06:00
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Load DMA cycle times into the chip ready for a DMA transfer
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* to occur.
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*/
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2006-08-30 22:03:49 -06:00
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2006-11-03 06:18:06 -07:00
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static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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2006-08-29 16:12:40 -06:00
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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2007-03-03 20:48:08 -07:00
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int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
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2006-08-29 16:12:40 -06:00
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static u8 udma_timing[6][2] = {
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{ 0x60, 0x03 }, /* 33 Mhz Clock */
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{ 0x40, 0x02 },
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{ 0x20, 0x01 },
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{ 0x40, 0x02 }, /* 66 Mhz Clock */
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{ 0x20, 0x01 },
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2006-08-30 22:03:49 -06:00
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{ 0x20, 0x01 }
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2006-08-29 16:12:40 -06:00
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};
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2007-03-03 20:48:08 -07:00
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static u8 mdma_timing[3][2] = {
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{ 0xe0, 0x0f },
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2007-09-26 08:23:17 -06:00
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{ 0x60, 0x04 },
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{ 0x60, 0x03 },
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2007-03-03 20:48:08 -07:00
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};
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2006-08-29 16:12:40 -06:00
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u8 r_bp, r_cp;
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2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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pci_read_config_byte(pdev, port + 1, &r_bp);
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pci_read_config_byte(pdev, port + 2, &r_cp);
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2006-08-30 22:03:49 -06:00
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2007-03-03 20:48:08 -07:00
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r_bp &= ~0xE0;
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2006-08-29 16:12:40 -06:00
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r_cp &= ~0x0F;
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2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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if (adev->dma_mode >= XFER_UDMA_0) {
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int speed = adev->dma_mode - XFER_UDMA_0;
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r_bp |= udma_timing[speed][0];
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r_cp |= udma_timing[speed][1];
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2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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} else {
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int speed = adev->dma_mode - XFER_MW_DMA_0;
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2007-03-03 20:48:08 -07:00
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r_bp |= mdma_timing[speed][0];
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r_cp |= mdma_timing[speed][1];
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2006-08-29 16:12:40 -06:00
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}
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pci_write_config_byte(pdev, port + 1, r_bp);
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pci_write_config_byte(pdev, port + 2, r_cp);
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2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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}
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/**
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* pdc2026x_bmdma_start - DMA engine begin
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* @qc: ATA command
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*
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* In UDMA3 or higher we have to clock switch for the duration of the
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* DMA transfer sequence.
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2007-09-26 08:23:17 -06:00
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*
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* Note: The host lock held by the libata layer protects
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* us from two channels both trying to set DMA bits at once
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2006-08-29 16:12:40 -06:00
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*/
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2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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struct ata_taskfile *tf = &qc->tf;
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int sel66 = ap->port_no ? 0x08: 0x02;
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2007-01-31 23:06:36 -07:00
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void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
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void __iomem *clock = master + 0x11;
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void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
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2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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u32 len;
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2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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/* Check we keep host level locking here */
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2009-04-20 14:31:25 -06:00
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if (adev->dma_mode > XFER_UDMA_2)
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2007-01-31 23:06:36 -07:00
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iowrite8(ioread8(clock) | sel66, clock);
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2006-08-29 16:12:40 -06:00
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else
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2007-01-31 23:06:36 -07:00
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iowrite8(ioread8(clock) & ~sel66, clock);
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2006-08-29 16:12:40 -06:00
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2006-08-30 22:03:49 -06:00
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/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
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2006-08-29 16:12:40 -06:00
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and move to qc_issue ? */
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2006-11-03 06:18:06 -07:00
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pdc202xx_set_dmamode(ap, qc->dev);
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2006-08-29 16:12:40 -06:00
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/* Cases the state machine will not complete correctly without help */
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2007-12-18 14:34:43 -07:00
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if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATAPI_PROT_DMA) {
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2007-03-23 12:57:23 -06:00
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len = qc->nbytes / 2;
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2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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if (tf->flags & ATA_TFLAG_WRITE)
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len |= 0x06000000;
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else
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len |= 0x05000000;
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2006-08-30 22:03:49 -06:00
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2007-01-31 23:06:36 -07:00
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iowrite32(len, atapi_reg);
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2006-08-29 16:12:40 -06:00
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}
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2006-08-30 22:03:49 -06:00
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/* Activate DMA */
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2006-08-29 16:12:40 -06:00
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ata_bmdma_start(qc);
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}
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/**
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* pdc2026x_bmdma_end - DMA engine stop
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* @qc: ATA command
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*
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* After a DMA completes we need to put the clock back to 33MHz for
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* PIO timings.
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2007-09-26 08:23:17 -06:00
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*
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* Note: The host lock held by the libata layer protects
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* us from two channels both trying to set DMA bits at once
|
2006-08-29 16:12:40 -06:00
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*/
|
2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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struct ata_taskfile *tf = &qc->tf;
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2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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int sel66 = ap->port_no ? 0x08: 0x02;
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/* The clock bits are in the same register for both channels */
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2007-01-31 23:06:36 -07:00
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void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
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void __iomem *clock = master + 0x11;
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void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
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2006-08-30 22:03:49 -06:00
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2006-08-29 16:12:40 -06:00
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/* Cases the state machine will not complete correctly */
|
2007-12-18 14:34:43 -07:00
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if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) {
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2007-01-31 23:06:36 -07:00
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iowrite32(0, atapi_reg);
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iowrite8(ioread8(clock) & ~sel66, clock);
|
2006-08-29 16:12:40 -06:00
|
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}
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/* Flip back to 33Mhz for PIO */
|
2009-04-20 14:31:25 -06:00
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if (adev->dma_mode > XFER_UDMA_2)
|
2007-01-31 23:06:36 -07:00
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iowrite8(ioread8(clock) & ~sel66, clock);
|
2006-08-29 16:12:40 -06:00
|
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ata_bmdma_stop(qc);
|
2008-01-03 17:08:49 -07:00
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pdc202xx_set_piomode(ap, adev);
|
2006-08-29 16:12:40 -06:00
|
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}
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|
|
/**
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* pdc2026x_dev_config - device setup hook
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* @adev: newly found device
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*
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|
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* Perform chip specific early setup. We need to lock the transfer
|
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|
|
* sizes to 8bit to avoid making the state engine on the 2026x cards
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* barf.
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*/
|
2006-08-30 22:03:49 -06:00
|
|
|
|
2007-03-01 17:56:15 -07:00
|
|
|
static void pdc2026x_dev_config(struct ata_device *adev)
|
2006-08-29 16:12:40 -06:00
|
|
|
{
|
|
|
|
adev->max_sectors = 256;
|
|
|
|
}
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|
|
|
|
2008-01-03 17:08:49 -07:00
|
|
|
static int pdc2026x_port_start(struct ata_port *ap)
|
|
|
|
{
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|
|
void __iomem *bmdma = ap->ioaddr.bmdma_addr;
|
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|
|
if (bmdma) {
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|
|
/* Enable burst mode */
|
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|
|
u8 burst = ioread8(bmdma + 0x1f);
|
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|
|
iowrite8(burst | 0x01, bmdma + 0x1f);
|
|
|
|
}
|
libata-sff: clean up BMDMA initialization
When BMDMA initialization failed or BMDMA was not available for
whatever reason, bmdma_addr was left at zero and used as an indication
that BMDMA shouldn't be used. This leads to the following problems.
p1. For BMDMA drivers which don't use traditional BMDMA register,
ata_bmdma_mode_filter() incorrectly inhibits DMA modes. Those
drivers either have to inherit from ata_sff_port_ops or clear
->mode_filter explicitly.
p2. non-BMDMA drivers call into BMDMA PRD table allocation. It
doesn't actually allocate PRD table if bmdma_addr is not
initialized but is still confusing.
p3. For BMDMA drivers which don't use traditional BMDMA register, some
methods might not be invoked as expected (e.g. bmdma_stop from
ata_sff_post_internal_cmd()).
p4. SFF drivers w/ custom DMA interface implement noop BMDMA ops
worrying libata core might call into one of them.
These problems are caused by the muddy line between SFF and BMDMA and
the assumption that all BMDMA controllers initialize bmdma_addr.
This patch fixes p1 and p2 by removing the bmdma_addr assumption and
moving prd allocation to BMDMA port start. Later patches will fix the
remaining issues.
This patch improves BMDMA initialization such that
* When BMDMA register initialization fails, falls back to PIO instead
of failing. ata_pci_bmdma_init() never fails now.
* When ata_pci_bmdma_init() falls back to PIO, it clears
ap->mwdma_mask and udma_mask instead of depending on
ata_bmdma_mode_filter(). This makes ata_bmdma_mode_filter()
unnecessary thus resolving p1.
* ata_port_start() which actually is BMDMA specific is moved to
ata_bmdma_port_start(). ata_port_start() and ata_sff_port_start()
are killed.
* ata_sff_port_start32() is moved and renamed to
ata_bmdma_port_start32().
Drivers which no longer call into PRD table allocation are...
pdc_adma, sata_inic162x, sata_qstor, sata_sx4, pata_cmd640 and all
drivers which inherit from ata_sff_port_ops.
pata_icside sets ->port_start to ATA_OP_NULL as it doesn't need PRD
but is a BMDMA controller and doesn't have custom port_start like
other such controllers.
Note that with the previous patch which makes all and only BMDMA
drivers inherit from ata_bmdma_port_ops, this change doesn't break
drivers which need PRD table.
Signed-off-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-05-10 13:41:34 -06:00
|
|
|
return ata_bmdma_port_start(ap);
|
2008-01-03 17:08:49 -07:00
|
|
|
}
|
|
|
|
|
2008-01-19 08:51:26 -07:00
|
|
|
/**
|
|
|
|
* pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
|
|
|
|
* @qc: Metadata associated with taskfile to check
|
|
|
|
*
|
|
|
|
* Just say no - not supported on older Promise.
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*
|
|
|
|
* RETURNS: 0 when ATAPI DMA can be used
|
|
|
|
* 1 otherwise
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2006-11-03 06:18:06 -07:00
|
|
|
static struct scsi_host_template pdc202xx_sht = {
|
2008-03-24 21:22:49 -06:00
|
|
|
ATA_BMDMA_SHT(DRV_NAME),
|
2006-08-29 16:12:40 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct ata_port_operations pdc2024x_port_ops = {
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 21:22:49 -06:00
|
|
|
.inherits = &ata_bmdma_port_ops,
|
|
|
|
|
|
|
|
.cable_detect = ata_cable_40wire,
|
|
|
|
.set_piomode = pdc202xx_set_piomode,
|
|
|
|
.set_dmamode = pdc202xx_set_dmamode,
|
2010-02-13 06:35:53 -07:00
|
|
|
|
2010-02-13 15:43:17 -07:00
|
|
|
.sff_exec_command = pdc202xx_exec_command,
|
2010-10-08 08:57:45 -06:00
|
|
|
.sff_irq_check = pdc202xx_irq_check,
|
2006-08-30 22:03:49 -06:00
|
|
|
};
|
2006-08-29 16:12:40 -06:00
|
|
|
|
|
|
|
static struct ata_port_operations pdc2026x_port_ops = {
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 21:22:49 -06:00
|
|
|
.inherits = &pdc2024x_port_ops,
|
|
|
|
|
|
|
|
.check_atapi_dma = pdc2026x_check_atapi_dma,
|
|
|
|
.bmdma_start = pdc2026x_bmdma_start,
|
|
|
|
.bmdma_stop = pdc2026x_bmdma_stop,
|
|
|
|
|
|
|
|
.cable_detect = pdc2026x_cable_detect,
|
|
|
|
.dev_config = pdc2026x_dev_config,
|
|
|
|
|
|
|
|
.port_start = pdc2026x_port_start,
|
2010-02-13 15:43:17 -07:00
|
|
|
|
|
|
|
.sff_exec_command = pdc202xx_exec_command,
|
2010-10-08 08:57:45 -06:00
|
|
|
.sff_irq_check = pdc202xx_irq_check,
|
2006-08-30 22:03:49 -06:00
|
|
|
};
|
2006-08-29 16:12:40 -06:00
|
|
|
|
2006-11-03 06:18:06 -07:00
|
|
|
static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
2006-08-29 16:12:40 -06:00
|
|
|
{
|
2007-05-04 04:43:58 -06:00
|
|
|
static const struct ata_port_info info[3] = {
|
2006-08-29 16:12:40 -06:00
|
|
|
{
|
2007-05-28 04:59:48 -06:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 14:38:24 -06:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2006-08-29 16:12:40 -06:00
|
|
|
.udma_mask = ATA_UDMA2,
|
|
|
|
.port_ops = &pdc2024x_port_ops
|
2006-08-30 22:03:49 -06:00
|
|
|
},
|
2006-08-29 16:12:40 -06:00
|
|
|
{
|
2007-05-28 04:59:48 -06:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 14:38:24 -06:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2006-08-29 16:12:40 -06:00
|
|
|
.udma_mask = ATA_UDMA4,
|
|
|
|
.port_ops = &pdc2026x_port_ops
|
|
|
|
},
|
|
|
|
{
|
2007-05-28 04:59:48 -06:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 14:38:24 -06:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2006-08-29 16:12:40 -06:00
|
|
|
.udma_mask = ATA_UDMA5,
|
|
|
|
.port_ops = &pdc2026x_port_ops
|
|
|
|
}
|
2006-08-30 22:03:49 -06:00
|
|
|
|
2006-08-29 16:12:40 -06:00
|
|
|
};
|
2007-05-04 04:43:58 -06:00
|
|
|
const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
|
2006-08-30 22:03:49 -06:00
|
|
|
|
2006-08-29 16:12:40 -06:00
|
|
|
if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
|
|
|
|
struct pci_dev *bridge = dev->bus->self;
|
|
|
|
/* Don't grab anything behind a Promise I2O RAID */
|
|
|
|
if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
|
2007-10-25 18:47:30 -06:00
|
|
|
if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
|
2006-08-29 16:12:40 -06:00
|
|
|
return -ENODEV;
|
2007-10-25 18:47:30 -06:00
|
|
|
if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
|
2006-08-29 16:12:40 -06:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
}
|
2010-05-19 14:10:22 -06:00
|
|
|
return ata_pci_bmdma_init_one(dev, ppi, &pdc202xx_sht, NULL, 0);
|
2006-08-29 16:12:40 -06:00
|
|
|
}
|
|
|
|
|
2006-11-03 06:18:06 -07:00
|
|
|
static const struct pci_device_id pdc202xx[] = {
|
2006-09-28 18:21:59 -06:00
|
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
|
|
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
|
|
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
|
|
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
|
|
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
|
|
|
|
|
|
|
|
{ },
|
2006-08-29 16:12:40 -06:00
|
|
|
};
|
|
|
|
|
2006-11-03 06:18:06 -07:00
|
|
|
static struct pci_driver pdc202xx_pci_driver = {
|
2006-09-28 18:21:59 -06:00
|
|
|
.name = DRV_NAME,
|
2006-11-03 06:18:06 -07:00
|
|
|
.id_table = pdc202xx,
|
|
|
|
.probe = pdc202xx_init_one,
|
2006-11-27 09:27:20 -07:00
|
|
|
.remove = ata_pci_remove_one,
|
2007-03-02 01:31:26 -07:00
|
|
|
#ifdef CONFIG_PM
|
2006-11-27 09:27:20 -07:00
|
|
|
.suspend = ata_pci_device_suspend,
|
|
|
|
.resume = ata_pci_device_resume,
|
2007-03-02 01:31:26 -07:00
|
|
|
#endif
|
2006-08-29 16:12:40 -06:00
|
|
|
};
|
|
|
|
|
2012-04-18 23:43:05 -06:00
|
|
|
module_pci_driver(pdc202xx_pci_driver);
|
2006-08-29 16:12:40 -06:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
|
|
MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
|
|
|
|
MODULE_LICENSE("GPL");
|
2006-11-03 06:18:06 -07:00
|
|
|
MODULE_DEVICE_TABLE(pci, pdc202xx);
|
2006-08-29 16:12:40 -06:00
|
|
|
MODULE_VERSION(DRV_VERSION);
|