f9da455b93
Pull networking updates from David Miller:
1) Seccomp BPF filters can now be JIT'd, from Alexei Starovoitov.
2) Multiqueue support in xen-netback and xen-netfront, from Andrew J
Benniston.
3) Allow tweaking of aggregation settings in cdc_ncm driver, from Bjørn
Mork.
4) BPF now has a "random" opcode, from Chema Gonzalez.
5) Add more BPF documentation and improve test framework, from Daniel
Borkmann.
6) Support TCP fastopen over ipv6, from Daniel Lee.
7) Add software TSO helper functions and use them to support software
TSO in mvneta and mv643xx_eth drivers. From Ezequiel Garcia.
8) Support software TSO in fec driver too, from Nimrod Andy.
9) Add Broadcom SYSTEMPORT driver, from Florian Fainelli.
10) Handle broadcasts more gracefully over macvlan when there are large
numbers of interfaces configured, from Herbert Xu.
11) Allow more control over fwmark used for non-socket based responses,
from Lorenzo Colitti.
12) Do TCP congestion window limiting based upon measurements, from Neal
Cardwell.
13) Support busy polling in SCTP, from Neal Horman.
14) Allow RSS key to be configured via ethtool, from Venkata Duvvuru.
15) Bridge promisc mode handling improvements from Vlad Yasevich.
16) Don't use inetpeer entries to implement ID generation any more, it
performs poorly, from Eric Dumazet.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1522 commits)
rtnetlink: fix userspace API breakage for iproute2 < v3.9.0
tcp: fixing TLP's FIN recovery
net: fec: Add software TSO support
net: fec: Add Scatter/gather support
net: fec: Increase buffer descriptor entry number
net: fec: Factorize feature setting
net: fec: Enable IP header hardware checksum
net: fec: Factorize the .xmit transmit function
bridge: fix compile error when compiling without IPv6 support
bridge: fix smatch warning / potential null pointer dereference
via-rhine: fix full-duplex with autoneg disable
bnx2x: Enlarge the dorq threshold for VFs
bnx2x: Check for UNDI in uncommon branch
bnx2x: Fix 1G-baseT link
bnx2x: Fix link for KR with swapped polarity lane
sctp: Fix sk_ack_backlog wrap-around problem
net/core: Add VF link state control policy
net/fsl: xgmac_mdio is dependent on OF_MDIO
net/fsl: Make xgmac_mdio read error message useful
net_sched: drr: warn when qdisc is not work conserving
...
140 lines
5.8 KiB
C
140 lines
5.8 KiB
C
/*
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* AM43XX Clock init
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*
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* Copyright (C) 2013 Texas Instruments, Inc
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* Tero Kristo (t-kristo@ti.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/ti.h>
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static struct ti_dt_clk am43xx_clks[] = {
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DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
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DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
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DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
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DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
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DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
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DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
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DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
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DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
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DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
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DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
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DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
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DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
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DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
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DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
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DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
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DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
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DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
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DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
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DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
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DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
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DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
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DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
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DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
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DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
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DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
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DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
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DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
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DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
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DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
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DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
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DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
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DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
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DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
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DT_CLK(NULL, "sha0_fck", "sha0_fck"),
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DT_CLK(NULL, "aes0_fck", "aes0_fck"),
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DT_CLK(NULL, "timer1_fck", "timer1_fck"),
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DT_CLK(NULL, "timer2_fck", "timer2_fck"),
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DT_CLK(NULL, "timer3_fck", "timer3_fck"),
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DT_CLK(NULL, "timer4_fck", "timer4_fck"),
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DT_CLK(NULL, "timer5_fck", "timer5_fck"),
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DT_CLK(NULL, "timer6_fck", "timer6_fck"),
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DT_CLK(NULL, "timer7_fck", "timer7_fck"),
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DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
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DT_CLK(NULL, "l3_gclk", "l3_gclk"),
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DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
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DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
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DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
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DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
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DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
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DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
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DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
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DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
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DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
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DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
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DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
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DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
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DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
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DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
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DT_CLK(NULL, "mmc_clk", "mmc_clk"),
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DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
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DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
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DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
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DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
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DT_CLK(NULL, "sysclk_div", "sysclk_div"),
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DT_CLK(NULL, "disp_clk", "disp_clk"),
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DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"),
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DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"),
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DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"),
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DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"),
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DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"),
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DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"),
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DT_CLK(NULL, "timer8_fck", "timer8_fck"),
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DT_CLK(NULL, "timer9_fck", "timer9_fck"),
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DT_CLK(NULL, "timer10_fck", "timer10_fck"),
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DT_CLK(NULL, "timer11_fck", "timer11_fck"),
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DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"),
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DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"),
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DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
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DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"),
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DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"),
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DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"),
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DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"),
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DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
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DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
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DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
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DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
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DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
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DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
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DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"),
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DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"),
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DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"),
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{ .node_name = NULL },
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};
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int __init am43xx_dt_clk_init(void)
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{
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struct clk *clk1, *clk2;
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ti_dt_clocks_register(am43xx_clks);
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omap2_clk_disable_autoidle_all();
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/*
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* cpsw_cpts_rft_clk has got the choice of 3 clocksources
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* dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.
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* By default dpll_core_m4_ck is selected, witn this as clock
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* source the CPTS doesnot work properly. It gives clockcheck errors
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* while running PTP.
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* clockcheck: clock jumped backward or running slower than expected!
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* By selecting dpll_core_m5_ck as the clocksource fixes this issue.
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* In AM335x dpll_core_m5_ck is the default clocksource.
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*/
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clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk");
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clk2 = clk_get_sys(NULL, "dpll_core_m5_ck");
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clk_set_parent(clk1, clk2);
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return 0;
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}
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