f946738ca8
This patch adds support for checking if the digital baseband (DB) System-on-Chip (aka "cpu) ASIC hardware version is 1.0, 1.1 or 2.0. We print the result in the bootlog, the functions are then used for runtime decisions based on hardware version. Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
145 lines
5.6 KiB
C
145 lines
5.6 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef __MACH_DB8500_REGS_H
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#define __MACH_DB8500_REGS_H
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/* Base address and bank offsets for ESRAM */
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#define U8500_ESRAM_BASE 0x40000000
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#define U8500_ESRAM_BANK_SIZE 0x00020000
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#define U8500_ESRAM_BANK0 U8500_ESRAM_BASE
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#define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE)
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#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
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#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
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#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
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/* Use bank 4 for DMA LCPA */
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#define U8500_DMA_LCPA_BASE U8500_ESRAM_BANK4
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#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000)
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#define U8500_PER3_BASE 0x80000000
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#define U8500_STM_BASE 0x80100000
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#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
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#define U8500_PER2_BASE 0x80110000
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#define U8500_PER1_BASE 0x80120000
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#define U8500_B2R2_BASE 0x80130000
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#define U8500_HSEM_BASE 0x80140000
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#define U8500_PER4_BASE 0x80150000
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#define U8500_ICN_BASE 0x81000000
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#define U8500_BOOT_ROM_BASE 0x90000000
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#define U8500_PER6_BASE 0xa03c0000
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#define U8500_PER5_BASE 0xa03e0000
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#define U8500_PER7_BASE_ED 0xa03d0000
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#define U8500_SVA_BASE 0xa0100000
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#define U8500_SIA_BASE 0xa0200000
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#define U8500_SGA_BASE 0xa0300000
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#define U8500_MCDE_BASE 0xa0350000
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#define U8500_DMA_BASE_ED 0xa0362000
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#define U8500_DMA_BASE 0x801C0000 /* v1 */
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#define U8500_SBAG_BASE 0xa0390000
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#define U8500_SCU_BASE 0xa0410000
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#define U8500_GIC_CPU_BASE 0xa0410100
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#define U8500_TWD_BASE 0xa0410600
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#define U8500_GIC_DIST_BASE 0xa0411000
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#define U8500_L2CC_BASE 0xa0412000
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#define U8500_MODEM_I2C 0xb7e02000
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#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
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#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000)
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#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
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#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
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/* per7 base addressess */
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#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000)
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#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000)
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#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000)
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#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000)
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#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000)
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#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
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#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
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/* per6 base addressess */
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#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
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#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
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#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
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#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
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#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
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#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
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#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
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#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
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#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
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/* per5 base addressess */
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#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
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#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
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/* per4 base addressess */
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#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000)
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#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000)
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#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000)
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#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000)
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#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000)
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#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000)
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#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
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#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
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#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000)
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/* per3 base addresses */
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#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
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#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
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#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
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#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
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#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
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#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
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#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
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#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
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#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
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/* per2 base addressess */
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#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
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#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
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#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
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#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
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#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
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#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
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#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
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#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
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#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
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#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
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#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
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#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
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/* per1 base addresses */
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#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
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#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
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#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
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#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
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#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
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#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
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#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000)
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#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000)
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#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
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#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040
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#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE
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#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80)
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#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE
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#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80)
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#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100)
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#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180)
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#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE
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#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
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#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE
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#endif
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