2bb49f1b9f
cx18: Adjust outgoing mailbox timeouts and remove statistics logging. This saves some wasted storage in struct cx18 for each card. Cutting the outgoing mailbox timeouts in half from the previous value appears to be safe with MythTV. Got rid of interrupted case code path after a wait uninterruptable returns. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
97 lines
2.7 KiB
C
97 lines
2.7 KiB
C
/*
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* cx18 driver PCI memory mapped IO access routines
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*
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* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
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* Copyright (C) 2008 Andy Walls <awalls@radix.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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* 02111-1307 USA
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*/
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#include "cx18-driver.h"
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#include "cx18-io.h"
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#include "cx18-irq.h"
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void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
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{
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u8 __iomem *dst = addr;
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u16 val2 = val | (val << 8);
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u32 val4 = val2 | (val2 << 16);
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/* Align writes on the CX23418's addresses */
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if ((count > 0) && ((unsigned long)dst & 1)) {
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cx18_writeb(cx, (u8) val, dst);
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count--;
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dst++;
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}
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if ((count > 1) && ((unsigned long)dst & 2)) {
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cx18_writew(cx, val2, dst);
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count -= 2;
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dst += 2;
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}
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while (count > 3) {
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cx18_writel(cx, val4, dst);
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count -= 4;
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dst += 4;
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}
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if (count > 1) {
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cx18_writew(cx, val2, dst);
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count -= 2;
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dst += 2;
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}
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if (count > 0)
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cx18_writeb(cx, (u8) val, dst);
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}
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void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
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{
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cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
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cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
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cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
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}
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void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
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{
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cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
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cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
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}
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void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
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{
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cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
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cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val;
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cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
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}
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void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
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{
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cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
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cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
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}
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void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
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{
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u32 r;
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r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
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cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
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}
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void cx18_setup_page(struct cx18 *cx, u32 addr)
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{
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u32 val;
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val = cx18_read_reg(cx, 0xD000F8);
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val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
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cx18_write_reg(cx, val, 0xD000F8);
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}
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