4fa6b9c5dc
The ioapic acknowledge path translates interrupt vectors to irqs. It currently uses a first match algorithm, stopping when it finds the first redirection table entry containing the vector. That fails however if the guest changes the irq to a different line, leaving the old redirection table entry in place (though masked). Result is interrupts not making it to the guest. Fix by always scanning the entire redirection table. Signed-off-by: Avi Kivity <avi@qumranet.com>
403 lines
9.8 KiB
C
403 lines
9.8 KiB
C
/*
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* Copyright (C) 2001 MandrakeSoft S.A.
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*
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* MandrakeSoft S.A.
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* 43, rue d'Aboukir
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* 75002 Paris - France
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* http://www.linux-mandrake.com/
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* http://www.mandrakesoft.com/
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Yunhong Jiang <yunhong.jiang@intel.com>
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* Yaozu (Eddie) Dong <eddie.dong@intel.com>
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* Based on Xen 3.1 code.
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*/
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#include <linux/kvm_host.h>
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#include <linux/kvm.h>
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#include <linux/mm.h>
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#include <linux/highmem.h>
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#include <linux/smp.h>
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#include <linux/hrtimer.h>
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#include <linux/io.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/current.h>
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#include "ioapic.h"
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#include "lapic.h"
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#if 0
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#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
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#else
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#define ioapic_debug(fmt, arg...)
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#endif
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static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
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static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
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unsigned long addr,
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unsigned long length)
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{
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unsigned long result = 0;
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switch (ioapic->ioregsel) {
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case IOAPIC_REG_VERSION:
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result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
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| (IOAPIC_VERSION_ID & 0xff));
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break;
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case IOAPIC_REG_APIC_ID:
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case IOAPIC_REG_ARB_ID:
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result = ((ioapic->id & 0xf) << 24);
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break;
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default:
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{
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u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
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u64 redir_content;
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ASSERT(redir_index < IOAPIC_NUM_PINS);
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redir_content = ioapic->redirtbl[redir_index].bits;
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result = (ioapic->ioregsel & 0x1) ?
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(redir_content >> 32) & 0xffffffff :
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redir_content & 0xffffffff;
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break;
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}
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}
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return result;
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}
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static void ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
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{
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union ioapic_redir_entry *pent;
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pent = &ioapic->redirtbl[idx];
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if (!pent->fields.mask) {
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int injected = ioapic_deliver(ioapic, idx);
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if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
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pent->fields.remote_irr = 1;
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}
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if (!pent->fields.trig_mode)
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ioapic->irr &= ~(1 << idx);
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}
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static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
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{
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unsigned index;
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switch (ioapic->ioregsel) {
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case IOAPIC_REG_VERSION:
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/* Writes are ignored. */
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break;
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case IOAPIC_REG_APIC_ID:
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ioapic->id = (val >> 24) & 0xf;
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break;
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case IOAPIC_REG_ARB_ID:
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break;
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default:
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index = (ioapic->ioregsel - 0x10) >> 1;
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ioapic_debug("change redir index %x val %x\n", index, val);
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if (index >= IOAPIC_NUM_PINS)
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return;
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if (ioapic->ioregsel & 1) {
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ioapic->redirtbl[index].bits &= 0xffffffff;
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ioapic->redirtbl[index].bits |= (u64) val << 32;
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} else {
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ioapic->redirtbl[index].bits &= ~0xffffffffULL;
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ioapic->redirtbl[index].bits |= (u32) val;
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ioapic->redirtbl[index].fields.remote_irr = 0;
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}
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if (ioapic->irr & (1 << index))
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ioapic_service(ioapic, index);
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break;
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}
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}
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static int ioapic_inj_irq(struct kvm_ioapic *ioapic,
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struct kvm_vcpu *vcpu,
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u8 vector, u8 trig_mode, u8 delivery_mode)
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{
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ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode,
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delivery_mode);
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ASSERT((delivery_mode == IOAPIC_FIXED) ||
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(delivery_mode == IOAPIC_LOWEST_PRIORITY));
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return kvm_apic_set_irq(vcpu, vector, trig_mode);
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}
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static u32 ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest,
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u8 dest_mode)
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{
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u32 mask = 0;
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int i;
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struct kvm *kvm = ioapic->kvm;
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struct kvm_vcpu *vcpu;
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ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode);
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if (dest_mode == 0) { /* Physical mode. */
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if (dest == 0xFF) { /* Broadcast. */
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for (i = 0; i < KVM_MAX_VCPUS; ++i)
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if (kvm->vcpus[i] && kvm->vcpus[i]->arch.apic)
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mask |= 1 << i;
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return mask;
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}
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for (i = 0; i < KVM_MAX_VCPUS; ++i) {
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vcpu = kvm->vcpus[i];
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if (!vcpu)
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continue;
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if (kvm_apic_match_physical_addr(vcpu->arch.apic, dest)) {
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if (vcpu->arch.apic)
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mask = 1 << i;
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break;
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}
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}
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} else if (dest != 0) /* Logical mode, MDA non-zero. */
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for (i = 0; i < KVM_MAX_VCPUS; ++i) {
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vcpu = kvm->vcpus[i];
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if (!vcpu)
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continue;
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if (vcpu->arch.apic &&
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kvm_apic_match_logical_addr(vcpu->arch.apic, dest))
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mask |= 1 << vcpu->vcpu_id;
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}
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ioapic_debug("mask %x\n", mask);
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return mask;
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}
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static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
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{
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u8 dest = ioapic->redirtbl[irq].fields.dest_id;
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u8 dest_mode = ioapic->redirtbl[irq].fields.dest_mode;
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u8 delivery_mode = ioapic->redirtbl[irq].fields.delivery_mode;
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u8 vector = ioapic->redirtbl[irq].fields.vector;
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u8 trig_mode = ioapic->redirtbl[irq].fields.trig_mode;
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u32 deliver_bitmask;
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struct kvm_vcpu *vcpu;
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int vcpu_id, r = 0;
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ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
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"vector=%x trig_mode=%x\n",
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dest, dest_mode, delivery_mode, vector, trig_mode);
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deliver_bitmask = ioapic_get_delivery_bitmask(ioapic, dest, dest_mode);
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if (!deliver_bitmask) {
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ioapic_debug("no target on destination\n");
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return 0;
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}
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switch (delivery_mode) {
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case IOAPIC_LOWEST_PRIORITY:
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vcpu = kvm_get_lowest_prio_vcpu(ioapic->kvm, vector,
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deliver_bitmask);
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#ifdef CONFIG_X86
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if (irq == 0)
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vcpu = ioapic->kvm->vcpus[0];
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#endif
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if (vcpu != NULL)
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r = ioapic_inj_irq(ioapic, vcpu, vector,
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trig_mode, delivery_mode);
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else
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ioapic_debug("null lowest prio vcpu: "
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"mask=%x vector=%x delivery_mode=%x\n",
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deliver_bitmask, vector, IOAPIC_LOWEST_PRIORITY);
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break;
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case IOAPIC_FIXED:
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#ifdef CONFIG_X86
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if (irq == 0)
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deliver_bitmask = 1;
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#endif
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for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
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if (!(deliver_bitmask & (1 << vcpu_id)))
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continue;
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deliver_bitmask &= ~(1 << vcpu_id);
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vcpu = ioapic->kvm->vcpus[vcpu_id];
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if (vcpu) {
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r = ioapic_inj_irq(ioapic, vcpu, vector,
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trig_mode, delivery_mode);
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}
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}
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break;
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/* TODO: NMI */
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default:
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printk(KERN_WARNING "Unsupported delivery mode %d\n",
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delivery_mode);
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break;
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}
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return r;
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}
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void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
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{
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u32 old_irr = ioapic->irr;
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u32 mask = 1 << irq;
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union ioapic_redir_entry entry;
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if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
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entry = ioapic->redirtbl[irq];
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level ^= entry.fields.polarity;
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if (!level)
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ioapic->irr &= ~mask;
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else {
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ioapic->irr |= mask;
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if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
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|| !entry.fields.remote_irr)
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ioapic_service(ioapic, irq);
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}
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}
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}
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static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int gsi)
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{
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union ioapic_redir_entry *ent;
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ent = &ioapic->redirtbl[gsi];
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ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
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ent->fields.remote_irr = 0;
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if (!ent->fields.mask && (ioapic->irr & (1 << gsi)))
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ioapic_deliver(ioapic, gsi);
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}
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void kvm_ioapic_update_eoi(struct kvm *kvm, int vector)
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{
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struct kvm_ioapic *ioapic = kvm->arch.vioapic;
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int i;
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for (i = 0; i < IOAPIC_NUM_PINS; i++)
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if (ioapic->redirtbl[i].fields.vector == vector)
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__kvm_ioapic_update_eoi(ioapic, i);
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}
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static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr)
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{
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struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
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return ((addr >= ioapic->base_address &&
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(addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
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}
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static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
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void *val)
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{
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struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
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u32 result;
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ioapic_debug("addr %lx\n", (unsigned long)addr);
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ASSERT(!(addr & 0xf)); /* check alignment */
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addr &= 0xff;
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switch (addr) {
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case IOAPIC_REG_SELECT:
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result = ioapic->ioregsel;
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break;
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case IOAPIC_REG_WINDOW:
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result = ioapic_read_indirect(ioapic, addr, len);
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break;
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default:
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result = 0;
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break;
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}
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switch (len) {
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case 8:
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*(u64 *) val = result;
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break;
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case 1:
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case 2:
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case 4:
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memcpy(val, (char *)&result, len);
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break;
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default:
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printk(KERN_WARNING "ioapic: wrong length %d\n", len);
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}
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}
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static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
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const void *val)
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{
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struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
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u32 data;
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ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
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(void*)addr, len, val);
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ASSERT(!(addr & 0xf)); /* check alignment */
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if (len == 4 || len == 8)
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data = *(u32 *) val;
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else {
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printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
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return;
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}
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addr &= 0xff;
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switch (addr) {
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case IOAPIC_REG_SELECT:
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ioapic->ioregsel = data;
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break;
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case IOAPIC_REG_WINDOW:
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ioapic_write_indirect(ioapic, data);
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break;
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#ifdef CONFIG_IA64
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case IOAPIC_REG_EOI:
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kvm_ioapic_update_eoi(ioapic->kvm, data);
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break;
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#endif
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default:
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break;
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}
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}
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void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
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{
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int i;
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for (i = 0; i < IOAPIC_NUM_PINS; i++)
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ioapic->redirtbl[i].fields.mask = 1;
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ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
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ioapic->ioregsel = 0;
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ioapic->irr = 0;
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ioapic->id = 0;
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}
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int kvm_ioapic_init(struct kvm *kvm)
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{
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struct kvm_ioapic *ioapic;
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ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
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if (!ioapic)
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return -ENOMEM;
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kvm->arch.vioapic = ioapic;
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kvm_ioapic_reset(ioapic);
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ioapic->dev.read = ioapic_mmio_read;
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ioapic->dev.write = ioapic_mmio_write;
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ioapic->dev.in_range = ioapic_in_range;
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ioapic->dev.private = ioapic;
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ioapic->kvm = kvm;
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kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
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return 0;
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}
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