f65aad4177
Drivers for EDAC on Cavium. Supported subsystems are: o CPU primary caches. These are parity protected only, so only error reporting. o Second level cache - ECC protected, provides SECDED. o Memory: ECC / SECDEC if used with suitable DRAM modules. The driver will will only initialize if ECC is enabled on a system so is safe to run on non-ECC memory. o PCI: Parity error reporting Since it is very hard to test this sort of code the implementation is very conservative and uses polling where possible for now. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reviewed-by: Borislav Petkov <borislav.petkov@amd.com>
140 lines
3.3 KiB
C
140 lines
3.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009 Wind River Systems,
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/edac.h>
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#include "edac_core.h"
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#include "edac_module.h"
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#include <asm/octeon/cvmx.h>
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#include <asm/mipsregs.h>
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#define EDAC_MOD_STR "octeon"
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extern int register_co_cache_error_notifier(struct notifier_block *nb);
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extern int unregister_co_cache_error_notifier(struct notifier_block *nb);
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extern unsigned long long cache_err_dcache[NR_CPUS];
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static struct edac_device_ctl_info *ed_cavium;
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/*
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* EDAC CPU cache error callback
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*
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*/
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static int co_cache_error_event(struct notifier_block *this,
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unsigned long event, void *ptr)
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{
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unsigned int core = cvmx_get_core_num();
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unsigned int cpu = smp_processor_id();
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uint64_t icache_err = read_octeon_c0_icacheerr();
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struct edac_device_ctl_info *ed = ed_cavium;
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edac_device_printk(ed, KERN_ERR,
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"Cache error exception on core %d / processor %d:\n",
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core, cpu);
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edac_device_printk(ed, KERN_ERR,
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"cp0_errorepc == %lx\n", read_c0_errorepc());
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if (icache_err & 1) {
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edac_device_printk(ed, KERN_ERR, "CacheErr (Icache) == %llx\n",
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(unsigned long long)icache_err);
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write_octeon_c0_icacheerr(0);
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edac_device_handle_ce(ed, 0, 0, ed->ctl_name);
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}
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if (cache_err_dcache[core] & 1) {
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edac_device_printk(ed, KERN_ERR, "CacheErr (Dcache) == %llx\n",
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(unsigned long long)cache_err_dcache[core]);
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cache_err_dcache[core] = 0;
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edac_device_handle_ue(ed, 0, 0, ed->ctl_name);
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}
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return NOTIFY_DONE;
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}
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static struct notifier_block co_cache_error_notifier = {
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.notifier_call = co_cache_error_event,
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};
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static int __devinit co_cache_error_probe(struct platform_device *pdev)
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{
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struct edac_device_ctl_info *ed;
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int res = 0;
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ed = edac_device_alloc_ctl_info(0, "cpu", 1, NULL, 0, 0, NULL, 0,
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edac_device_alloc_index());
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ed->dev = &pdev->dev;
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platform_set_drvdata(pdev, ed);
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ed->dev_name = dev_name(&pdev->dev);
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ed->mod_name = "octeon-cpu";
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ed->ctl_name = "co_cpu_err";
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if (edac_device_add_device(ed) > 0) {
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pr_err("%s: edac_device_add_device() failed\n", __func__);
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goto err;
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}
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register_co_cache_error_notifier(&co_cache_error_notifier);
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ed_cavium = ed;
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return 0;
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err:
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edac_device_free_ctl_info(ed);
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return res;
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}
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static int co_cache_error_remove(struct platform_device *pdev)
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{
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struct edac_device_ctl_info *ed = platform_get_drvdata(pdev);
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unregister_co_cache_error_notifier(&co_cache_error_notifier);
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ed_cavium = NULL;
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edac_device_del_device(&pdev->dev);
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edac_device_free_ctl_info(ed);
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return 0;
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}
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static struct platform_driver co_cache_error_driver = {
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.probe = co_cache_error_probe,
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.remove = co_cache_error_remove,
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.driver = {
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.name = "co_pc_edac",
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}
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};
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static int __init co_edac_init(void)
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{
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int ret;
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ret = platform_driver_register(&co_cache_error_driver);
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if (ret)
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pr_warning(EDAC_MOD_STR "CPU err failed to register\n");
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return ret;
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}
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static void __exit co_edac_exit(void)
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{
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platform_driver_unregister(&co_cache_error_driver);
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}
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module_init(co_edac_init);
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module_exit(co_edac_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
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