820 lines
23 KiB
C
820 lines
23 KiB
C
/*
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* intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets)
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*
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* (c) Copyright 2006-2007 Wim Van Sebroeck <wim@iguana.be>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
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* provide warranty for any of this software. This material is
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* provided "AS-IS" and at no charge.
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*
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* The TCO watchdog is implemented in the following I/O controller hubs:
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* (See the intel documentation on http://developer.intel.com.)
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* 82801AA (ICH) : document number 290655-003, 290677-014,
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* 82801AB (ICHO) : document number 290655-003, 290677-014,
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* 82801BA (ICH2) : document number 290687-002, 298242-027,
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* 82801BAM (ICH2-M) : document number 290687-002, 298242-027,
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* 82801CA (ICH3-S) : document number 290733-003, 290739-013,
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* 82801CAM (ICH3-M) : document number 290716-001, 290718-007,
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* 82801DB (ICH4) : document number 290744-001, 290745-020,
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* 82801DBM (ICH4-M) : document number 252337-001, 252663-005,
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* 82801E (C-ICH) : document number 273599-001, 273645-002,
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* 82801EB (ICH5) : document number 252516-001, 252517-003,
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* 82801ER (ICH5R) : document number 252516-001, 252517-003,
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* 82801FB (ICH6) : document number 301473-002, 301474-007,
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* 82801FR (ICH6R) : document number 301473-002, 301474-007,
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* 82801FBM (ICH6-M) : document number 301473-002, 301474-007,
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* 82801FW (ICH6W) : document number 301473-001, 301474-007,
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* 82801FRW (ICH6RW) : document number 301473-001, 301474-007,
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* 82801GB (ICH7) : document number 307013-002, 307014-009,
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* 82801GR (ICH7R) : document number 307013-002, 307014-009,
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* 82801GDH (ICH7DH) : document number 307013-002, 307014-009,
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* 82801GBM (ICH7-M) : document number 307013-002, 307014-009,
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* 82801GHM (ICH7-M DH) : document number 307013-002, 307014-009,
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* 82801HB (ICH8) : document number 313056-003, 313057-009,
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* 82801HR (ICH8R) : document number 313056-003, 313057-009,
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* 82801HBM (ICH8M) : document number 313056-003, 313057-009,
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* 82801HH (ICH8DH) : document number 313056-003, 313057-009,
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* 82801HO (ICH8DO) : document number 313056-003, 313057-009,
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* 82801HEM (ICH8M-E) : document number 313056-003, 313057-009,
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* 82801IB (ICH9) : document number 316972-001, 316973-006,
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* 82801IR (ICH9R) : document number 316972-001, 316973-006,
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* 82801IH (ICH9DH) : document number 316972-001, 316973-006,
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* 82801IO (ICH9DO) : document number 316972-001, 316973-006,
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* 6300ESB (6300ESB) : document number 300641-003, 300884-010,
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* 631xESB (631xESB) : document number 313082-001, 313075-005,
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* 632xESB (632xESB) : document number 313082-001, 313075-005
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*/
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/*
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* Includes, defines, variables, module parameters, ...
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*/
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/* Module and version information */
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#define DRV_NAME "iTCO_wdt"
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#define DRV_VERSION "1.03"
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#define DRV_RELDATE "30-Apr-2008"
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#define PFX DRV_NAME ": "
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/* Includes */
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#include <linux/module.h> /* For module specific items */
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#include <linux/moduleparam.h> /* For new moduleparam's */
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#include <linux/types.h> /* For standard types (like size_t) */
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#include <linux/errno.h> /* For the -ENODEV/... values */
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#include <linux/kernel.h> /* For printk/panic/... */
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#include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
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(WATCHDOG_MINOR) */
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#include <linux/watchdog.h> /* For the watchdog specific items */
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#include <linux/init.h> /* For __init/__exit/... */
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#include <linux/fs.h> /* For file operations */
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#include <linux/platform_device.h> /* For platform_driver framework */
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#include <linux/pci.h> /* For pci functions */
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#include <linux/ioport.h> /* For io-port access */
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#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
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#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
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#include <linux/io.h> /* For inb/outb/... */
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#include "iTCO_vendor.h"
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/* TCO related info */
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enum iTCO_chipsets {
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TCO_ICH = 0, /* ICH */
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TCO_ICH0, /* ICH0 */
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TCO_ICH2, /* ICH2 */
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TCO_ICH2M, /* ICH2-M */
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TCO_ICH3, /* ICH3-S */
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TCO_ICH3M, /* ICH3-M */
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TCO_ICH4, /* ICH4 */
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TCO_ICH4M, /* ICH4-M */
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TCO_CICH, /* C-ICH */
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TCO_ICH5, /* ICH5 & ICH5R */
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TCO_6300ESB, /* 6300ESB */
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TCO_ICH6, /* ICH6 & ICH6R */
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TCO_ICH6M, /* ICH6-M */
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TCO_ICH6W, /* ICH6W & ICH6RW */
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TCO_ICH7, /* ICH7 & ICH7R */
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TCO_ICH7M, /* ICH7-M */
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TCO_ICH7MDH, /* ICH7-M DH */
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TCO_ICH8, /* ICH8 & ICH8R */
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TCO_ICH8ME, /* ICH8M-E */
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TCO_ICH8DH, /* ICH8DH */
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TCO_ICH8DO, /* ICH8DO */
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TCO_ICH8M, /* ICH8M */
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TCO_ICH9, /* ICH9 */
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TCO_ICH9R, /* ICH9R */
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TCO_ICH9DH, /* ICH9DH */
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TCO_ICH9DO, /* ICH9DO */
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TCO_631XESB, /* 631xESB/632xESB */
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};
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static struct {
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char *name;
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unsigned int iTCO_version;
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} iTCO_chipset_info[] __devinitdata = {
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{"ICH", 1},
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{"ICH0", 1},
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{"ICH2", 1},
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{"ICH2-M", 1},
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{"ICH3-S", 1},
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{"ICH3-M", 1},
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{"ICH4", 1},
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{"ICH4-M", 1},
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{"C-ICH", 1},
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{"ICH5 or ICH5R", 1},
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{"6300ESB", 1},
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{"ICH6 or ICH6R", 2},
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{"ICH6-M", 2},
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{"ICH6W or ICH6RW", 2},
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{"ICH7 or ICH7R", 2},
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{"ICH7-M", 2},
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{"ICH7-M DH", 2},
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{"ICH8 or ICH8R", 2},
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{"ICH8M-E", 2},
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{"ICH8DH", 2},
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{"ICH8DO", 2},
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{"ICH8M", 2},
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{"ICH9", 2},
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{"ICH9R", 2},
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{"ICH9DH", 2},
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{"ICH9DO", 2},
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{"631xESB/632xESB", 2},
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{NULL, 0}
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};
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#define ITCO_PCI_DEVICE(dev, data) \
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.vendor = PCI_VENDOR_ID_INTEL, \
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.device = dev, \
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.subvendor = PCI_ANY_ID, \
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.subdevice = PCI_ANY_ID, \
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.class = 0, \
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.class_mask = 0, \
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.driver_data = data
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/*
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* This data only exists for exporting the supported PCI ids
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* via MODULE_DEVICE_TABLE. We do not actually register a
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* pci_driver, because the I/O Controller Hub has also other
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* functions that probably will be registered by other drivers.
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*/
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static struct pci_device_id iTCO_wdt_pci_tbl[] = {
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)},
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{ ITCO_PCI_DEVICE(0x2918, TCO_ICH9)},
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{ ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)},
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{ ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x2671, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x2672, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x2673, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x2674, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x2675, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x2676, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x2677, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x2678, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x2679, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x267a, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x267b, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x267c, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x267d, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x267e, TCO_631XESB)},
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{ ITCO_PCI_DEVICE(0x267f, TCO_631XESB)},
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{ 0, }, /* End of list */
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};
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MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
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/* Address definitions for the TCO */
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/* TCO base address */
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#define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60
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/* SMI Control and Enable Register */
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#define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30
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#define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Curr. Value */
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#define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */
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#define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */
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#define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */
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#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
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#define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */
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#define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */
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#define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */
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#define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */
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/* internal variables */
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static unsigned long is_active;
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static char expect_release;
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static struct { /* this is private data for the iTCO_wdt device */
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/* TCO version/generation */
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unsigned int iTCO_version;
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/* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
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unsigned long ACPIBASE;
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/* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
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unsigned long __iomem *gcs;
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/* the lock for io operations */
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spinlock_t io_lock;
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/* the PCI-device */
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struct pci_dev *pdev;
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} iTCO_wdt_private;
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/* the watchdog platform device */
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static struct platform_device *iTCO_wdt_platform_device;
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/* module parameters */
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#define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
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static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
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module_param(heartbeat, int, 0);
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MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
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static int nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, int, 0);
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MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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/*
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* Some TCO specific functions
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*/
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static inline unsigned int seconds_to_ticks(int seconds)
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{
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/* the internal timer is stored as ticks which decrement
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* every 0.6 seconds */
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return (seconds * 10) / 6;
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}
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static void iTCO_wdt_set_NO_REBOOT_bit(void)
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{
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u32 val32;
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/* Set the NO_REBOOT bit: this disables reboots */
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if (iTCO_wdt_private.iTCO_version == 2) {
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val32 = readl(iTCO_wdt_private.gcs);
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val32 |= 0x00000020;
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writel(val32, iTCO_wdt_private.gcs);
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} else if (iTCO_wdt_private.iTCO_version == 1) {
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pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
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val32 |= 0x00000002;
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pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
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}
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}
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static int iTCO_wdt_unset_NO_REBOOT_bit(void)
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{
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int ret = 0;
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u32 val32;
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/* Unset the NO_REBOOT bit: this enables reboots */
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if (iTCO_wdt_private.iTCO_version == 2) {
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val32 = readl(iTCO_wdt_private.gcs);
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val32 &= 0xffffffdf;
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writel(val32, iTCO_wdt_private.gcs);
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val32 = readl(iTCO_wdt_private.gcs);
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if (val32 & 0x00000020)
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ret = -EIO;
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} else if (iTCO_wdt_private.iTCO_version == 1) {
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pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
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val32 &= 0xfffffffd;
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pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
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pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
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if (val32 & 0x00000002)
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ret = -EIO;
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}
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return ret; /* returns: 0 = OK, -EIO = Error */
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}
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static int iTCO_wdt_start(void)
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{
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unsigned int val;
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spin_lock(&iTCO_wdt_private.io_lock);
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iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
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/* disable chipset's NO_REBOOT bit */
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if (iTCO_wdt_unset_NO_REBOOT_bit()) {
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spin_unlock(&iTCO_wdt_private.io_lock);
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printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
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return -EIO;
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}
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/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
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val = inw(TCO1_CNT);
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val &= 0xf7ff;
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outw(val, TCO1_CNT);
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val = inw(TCO1_CNT);
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spin_unlock(&iTCO_wdt_private.io_lock);
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if (val & 0x0800)
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return -1;
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return 0;
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}
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static int iTCO_wdt_stop(void)
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{
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unsigned int val;
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spin_lock(&iTCO_wdt_private.io_lock);
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iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
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/* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
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val = inw(TCO1_CNT);
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val |= 0x0800;
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outw(val, TCO1_CNT);
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val = inw(TCO1_CNT);
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/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
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iTCO_wdt_set_NO_REBOOT_bit();
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spin_unlock(&iTCO_wdt_private.io_lock);
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if ((val & 0x0800) == 0)
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return -1;
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return 0;
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}
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static int iTCO_wdt_keepalive(void)
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{
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spin_lock(&iTCO_wdt_private.io_lock);
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iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
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/* Reload the timer by writing to the TCO Timer Counter register */
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if (iTCO_wdt_private.iTCO_version == 2)
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outw(0x01, TCO_RLD);
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else if (iTCO_wdt_private.iTCO_version == 1)
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outb(0x01, TCO_RLD);
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spin_unlock(&iTCO_wdt_private.io_lock);
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return 0;
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}
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static int iTCO_wdt_set_heartbeat(int t)
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{
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unsigned int val16;
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unsigned char val8;
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unsigned int tmrval;
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tmrval = seconds_to_ticks(t);
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/* from the specs: */
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/* "Values of 0h-3h are ignored and should not be attempted" */
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if (tmrval < 0x04)
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return -EINVAL;
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if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
|
|
((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
|
|
return -EINVAL;
|
|
|
|
iTCO_vendor_pre_set_heartbeat(tmrval);
|
|
|
|
/* Write new heartbeat to watchdog */
|
|
if (iTCO_wdt_private.iTCO_version == 2) {
|
|
spin_lock(&iTCO_wdt_private.io_lock);
|
|
val16 = inw(TCOv2_TMR);
|
|
val16 &= 0xfc00;
|
|
val16 |= tmrval;
|
|
outw(val16, TCOv2_TMR);
|
|
val16 = inw(TCOv2_TMR);
|
|
spin_unlock(&iTCO_wdt_private.io_lock);
|
|
|
|
if ((val16 & 0x3ff) != tmrval)
|
|
return -EINVAL;
|
|
} else if (iTCO_wdt_private.iTCO_version == 1) {
|
|
spin_lock(&iTCO_wdt_private.io_lock);
|
|
val8 = inb(TCOv1_TMR);
|
|
val8 &= 0xc0;
|
|
val8 |= (tmrval & 0xff);
|
|
outb(val8, TCOv1_TMR);
|
|
val8 = inb(TCOv1_TMR);
|
|
spin_unlock(&iTCO_wdt_private.io_lock);
|
|
|
|
if ((val8 & 0x3f) != tmrval)
|
|
return -EINVAL;
|
|
}
|
|
|
|
heartbeat = t;
|
|
return 0;
|
|
}
|
|
|
|
static int iTCO_wdt_get_timeleft(int *time_left)
|
|
{
|
|
unsigned int val16;
|
|
unsigned char val8;
|
|
|
|
/* read the TCO Timer */
|
|
if (iTCO_wdt_private.iTCO_version == 2) {
|
|
spin_lock(&iTCO_wdt_private.io_lock);
|
|
val16 = inw(TCO_RLD);
|
|
val16 &= 0x3ff;
|
|
spin_unlock(&iTCO_wdt_private.io_lock);
|
|
|
|
*time_left = (val16 * 6) / 10;
|
|
} else if (iTCO_wdt_private.iTCO_version == 1) {
|
|
spin_lock(&iTCO_wdt_private.io_lock);
|
|
val8 = inb(TCO_RLD);
|
|
val8 &= 0x3f;
|
|
spin_unlock(&iTCO_wdt_private.io_lock);
|
|
|
|
*time_left = (val8 * 6) / 10;
|
|
} else
|
|
return -EINVAL;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* /dev/watchdog handling
|
|
*/
|
|
|
|
static int iTCO_wdt_open(struct inode *inode, struct file *file)
|
|
{
|
|
/* /dev/watchdog can only be opened once */
|
|
if (test_and_set_bit(0, &is_active))
|
|
return -EBUSY;
|
|
|
|
/*
|
|
* Reload and activate timer
|
|
*/
|
|
iTCO_wdt_keepalive();
|
|
iTCO_wdt_start();
|
|
return nonseekable_open(inode, file);
|
|
}
|
|
|
|
static int iTCO_wdt_release(struct inode *inode, struct file *file)
|
|
{
|
|
/*
|
|
* Shut off the timer.
|
|
*/
|
|
if (expect_release == 42) {
|
|
iTCO_wdt_stop();
|
|
} else {
|
|
printk(KERN_CRIT PFX
|
|
"Unexpected close, not stopping watchdog!\n");
|
|
iTCO_wdt_keepalive();
|
|
}
|
|
clear_bit(0, &is_active);
|
|
expect_release = 0;
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t iTCO_wdt_write(struct file *file, const char __user *data,
|
|
size_t len, loff_t *ppos)
|
|
{
|
|
/* See if we got the magic character 'V' and reload the timer */
|
|
if (len) {
|
|
if (!nowayout) {
|
|
size_t i;
|
|
|
|
/* note: just in case someone wrote the magic
|
|
character five months ago... */
|
|
expect_release = 0;
|
|
|
|
/* scan to see whether or not we got the
|
|
magic character */
|
|
for (i = 0; i != len; i++) {
|
|
char c;
|
|
if (get_user(c, data + i))
|
|
return -EFAULT;
|
|
if (c == 'V')
|
|
expect_release = 42;
|
|
}
|
|
}
|
|
|
|
/* someone wrote to us, we should reload the timer */
|
|
iTCO_wdt_keepalive();
|
|
}
|
|
return len;
|
|
}
|
|
|
|
static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd,
|
|
unsigned long arg)
|
|
{
|
|
int new_options, retval = -EINVAL;
|
|
int new_heartbeat;
|
|
void __user *argp = (void __user *)arg;
|
|
int __user *p = argp;
|
|
static struct watchdog_info ident = {
|
|
.options = WDIOF_SETTIMEOUT |
|
|
WDIOF_KEEPALIVEPING |
|
|
WDIOF_MAGICCLOSE,
|
|
.firmware_version = 0,
|
|
.identity = DRV_NAME,
|
|
};
|
|
|
|
switch (cmd) {
|
|
case WDIOC_GETSUPPORT:
|
|
return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
|
|
case WDIOC_GETSTATUS:
|
|
case WDIOC_GETBOOTSTATUS:
|
|
return put_user(0, p);
|
|
|
|
case WDIOC_SETOPTIONS:
|
|
{
|
|
if (get_user(new_options, p))
|
|
return -EFAULT;
|
|
|
|
if (new_options & WDIOS_DISABLECARD) {
|
|
iTCO_wdt_stop();
|
|
retval = 0;
|
|
}
|
|
if (new_options & WDIOS_ENABLECARD) {
|
|
iTCO_wdt_keepalive();
|
|
iTCO_wdt_start();
|
|
retval = 0;
|
|
}
|
|
return retval;
|
|
}
|
|
case WDIOC_KEEPALIVE:
|
|
iTCO_wdt_keepalive();
|
|
return 0;
|
|
|
|
case WDIOC_SETTIMEOUT:
|
|
{
|
|
if (get_user(new_heartbeat, p))
|
|
return -EFAULT;
|
|
if (iTCO_wdt_set_heartbeat(new_heartbeat))
|
|
return -EINVAL;
|
|
iTCO_wdt_keepalive();
|
|
/* Fall */
|
|
}
|
|
case WDIOC_GETTIMEOUT:
|
|
return put_user(heartbeat, p);
|
|
case WDIOC_GETTIMELEFT:
|
|
{
|
|
int time_left;
|
|
if (iTCO_wdt_get_timeleft(&time_left))
|
|
return -EINVAL;
|
|
return put_user(time_left, p);
|
|
}
|
|
default:
|
|
return -ENOTTY;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Kernel Interfaces
|
|
*/
|
|
|
|
static const struct file_operations iTCO_wdt_fops = {
|
|
.owner = THIS_MODULE,
|
|
.llseek = no_llseek,
|
|
.write = iTCO_wdt_write,
|
|
.unlocked_ioctl = iTCO_wdt_ioctl,
|
|
.open = iTCO_wdt_open,
|
|
.release = iTCO_wdt_release,
|
|
};
|
|
|
|
static struct miscdevice iTCO_wdt_miscdev = {
|
|
.minor = WATCHDOG_MINOR,
|
|
.name = "watchdog",
|
|
.fops = &iTCO_wdt_fops,
|
|
};
|
|
|
|
/*
|
|
* Init & exit routines
|
|
*/
|
|
|
|
static int __devinit iTCO_wdt_init(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent, struct platform_device *dev)
|
|
{
|
|
int ret;
|
|
u32 base_address;
|
|
unsigned long RCBA;
|
|
unsigned long val32;
|
|
|
|
/*
|
|
* Find the ACPI/PM base I/O address which is the base
|
|
* for the TCO registers (TCOBASE=ACPIBASE + 0x60)
|
|
* ACPIBASE is bits [15:7] from 0x40-0x43
|
|
*/
|
|
pci_read_config_dword(pdev, 0x40, &base_address);
|
|
base_address &= 0x0000ff80;
|
|
if (base_address == 0x00000000) {
|
|
/* Something's wrong here, ACPIBASE has to be set */
|
|
printk(KERN_ERR PFX "failed to get TCOBASE address\n");
|
|
pci_dev_put(pdev);
|
|
return -ENODEV;
|
|
}
|
|
iTCO_wdt_private.iTCO_version =
|
|
iTCO_chipset_info[ent->driver_data].iTCO_version;
|
|
iTCO_wdt_private.ACPIBASE = base_address;
|
|
iTCO_wdt_private.pdev = pdev;
|
|
|
|
/* Get the Memory-Mapped GCS register, we need it for the
|
|
NO_REBOOT flag (TCO v2). To get access to it you have to
|
|
read RCBA from PCI Config space 0xf0 and use it as base.
|
|
GCS = RCBA + ICH6_GCS(0x3410). */
|
|
if (iTCO_wdt_private.iTCO_version == 2) {
|
|
pci_read_config_dword(pdev, 0xf0, &base_address);
|
|
RCBA = base_address & 0xffffc000;
|
|
iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4);
|
|
}
|
|
|
|
/* Check chipset's NO_REBOOT bit */
|
|
if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
|
|
printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
|
|
ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
|
|
goto out;
|
|
}
|
|
|
|
/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
|
|
iTCO_wdt_set_NO_REBOOT_bit();
|
|
|
|
/* Set the TCO_EN bit in SMI_EN register */
|
|
if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
|
|
printk(KERN_ERR PFX
|
|
"I/O address 0x%04lx already in use\n", SMI_EN);
|
|
ret = -EIO;
|
|
goto out;
|
|
}
|
|
val32 = inl(SMI_EN);
|
|
val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
|
|
outl(val32, SMI_EN);
|
|
release_region(SMI_EN, 4);
|
|
|
|
/* The TCO I/O registers reside in a 32-byte range pointed to
|
|
by the TCOBASE value */
|
|
if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) {
|
|
printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n",
|
|
TCOBASE);
|
|
ret = -EIO;
|
|
goto out;
|
|
}
|
|
|
|
printk(KERN_INFO PFX
|
|
"Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
|
|
iTCO_chipset_info[ent->driver_data].name,
|
|
iTCO_chipset_info[ent->driver_data].iTCO_version,
|
|
TCOBASE);
|
|
|
|
/* Clear out the (probably old) status */
|
|
outb(0, TCO1_STS);
|
|
outb(3, TCO2_STS);
|
|
|
|
/* Make sure the watchdog is not running */
|
|
iTCO_wdt_stop();
|
|
|
|
/* Check that the heartbeat value is within it's range;
|
|
if not reset to the default */
|
|
if (iTCO_wdt_set_heartbeat(heartbeat)) {
|
|
iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
|
|
printk(KERN_INFO PFX "heartbeat value must be 2 < heartbeat < 39 (TCO v1) or 613 (TCO v2), using %d\n",
|
|
heartbeat);
|
|
}
|
|
|
|
ret = misc_register(&iTCO_wdt_miscdev);
|
|
if (ret != 0) {
|
|
printk(KERN_ERR PFX
|
|
"cannot register miscdev on minor=%d (err=%d)\n",
|
|
WATCHDOG_MINOR, ret);
|
|
goto unreg_region;
|
|
}
|
|
|
|
printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
|
|
heartbeat, nowayout);
|
|
|
|
return 0;
|
|
|
|
unreg_region:
|
|
release_region(TCOBASE, 0x20);
|
|
out:
|
|
if (iTCO_wdt_private.iTCO_version == 2)
|
|
iounmap(iTCO_wdt_private.gcs);
|
|
pci_dev_put(iTCO_wdt_private.pdev);
|
|
iTCO_wdt_private.ACPIBASE = 0;
|
|
return ret;
|
|
}
|
|
|
|
static void __devexit iTCO_wdt_cleanup(void)
|
|
{
|
|
/* Stop the timer before we leave */
|
|
if (!nowayout)
|
|
iTCO_wdt_stop();
|
|
|
|
/* Deregister */
|
|
misc_deregister(&iTCO_wdt_miscdev);
|
|
release_region(TCOBASE, 0x20);
|
|
if (iTCO_wdt_private.iTCO_version == 2)
|
|
iounmap(iTCO_wdt_private.gcs);
|
|
pci_dev_put(iTCO_wdt_private.pdev);
|
|
iTCO_wdt_private.ACPIBASE = 0;
|
|
}
|
|
|
|
static int __devinit iTCO_wdt_probe(struct platform_device *dev)
|
|
{
|
|
int found = 0;
|
|
struct pci_dev *pdev = NULL;
|
|
const struct pci_device_id *ent;
|
|
|
|
spin_lock_init(&iTCO_wdt_private.io_lock);
|
|
|
|
for_each_pci_dev(pdev) {
|
|
ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
|
|
if (ent) {
|
|
if (!(iTCO_wdt_init(pdev, ent, dev))) {
|
|
found++;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!found) {
|
|
printk(KERN_INFO PFX "No card detected\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __devexit iTCO_wdt_remove(struct platform_device *dev)
|
|
{
|
|
if (iTCO_wdt_private.ACPIBASE)
|
|
iTCO_wdt_cleanup();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void iTCO_wdt_shutdown(struct platform_device *dev)
|
|
{
|
|
iTCO_wdt_stop();
|
|
}
|
|
|
|
#define iTCO_wdt_suspend NULL
|
|
#define iTCO_wdt_resume NULL
|
|
|
|
static struct platform_driver iTCO_wdt_driver = {
|
|
.probe = iTCO_wdt_probe,
|
|
.remove = __devexit_p(iTCO_wdt_remove),
|
|
.shutdown = iTCO_wdt_shutdown,
|
|
.suspend = iTCO_wdt_suspend,
|
|
.resume = iTCO_wdt_resume,
|
|
.driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = DRV_NAME,
|
|
},
|
|
};
|
|
|
|
static int __init iTCO_wdt_init_module(void)
|
|
{
|
|
int err;
|
|
|
|
printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s (%s)\n",
|
|
DRV_VERSION, DRV_RELDATE);
|
|
|
|
err = platform_driver_register(&iTCO_wdt_driver);
|
|
if (err)
|
|
return err;
|
|
|
|
iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME,
|
|
-1, NULL, 0);
|
|
if (IS_ERR(iTCO_wdt_platform_device)) {
|
|
err = PTR_ERR(iTCO_wdt_platform_device);
|
|
goto unreg_platform_driver;
|
|
}
|
|
|
|
return 0;
|
|
|
|
unreg_platform_driver:
|
|
platform_driver_unregister(&iTCO_wdt_driver);
|
|
return err;
|
|
}
|
|
|
|
static void __exit iTCO_wdt_cleanup_module(void)
|
|
{
|
|
platform_device_unregister(iTCO_wdt_platform_device);
|
|
platform_driver_unregister(&iTCO_wdt_driver);
|
|
printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
|
|
}
|
|
|
|
module_init(iTCO_wdt_init_module);
|
|
module_exit(iTCO_wdt_cleanup_module);
|
|
|
|
MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
|
|
MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
|
|
MODULE_VERSION(DRV_VERSION);
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
|