b630a23a73
kernel cycle: Core: - The pin control Kconfig entry PINCTRL is now turned into a menuconfig option. This obviously has the implication of making the subsystem menu visible in menuconfig. This is happening because of two things: - Intel have started to deploy and depend on pin controllers in a way that is affecting users directly. This happens on the highly integrated laptop chipsets named after geographical places: baytrail, broxton, cannonlake, cedarfork, cherryview, denverton, geminilake, lewisburg, merrifield, sunrisepoint... It started a while back and now it is ever more evident that this is crucial infrastructure for x86 laptops and not an embedded obscurity anymore. Users need to be aware. - Pin control expanders on I2C and SPI that are arch-agnostic. Currently Semtech SX150X and Microchip MCP28x08 but more are expected. Users will have to be able to configure these in directly for their set-up. - Just go and select GPIOLIB now that we made sure that GPIOLIB is a very vanilla subsystem. Do not depend on it, if we need it, select it. - Exposing the pin control subsystem in menuconfig uncovered a bunch of obscure bugs that are now hopefully fixed, all more or less pertaining to Blackfin. - Unified namespace for cross-calls between pin control and GPIO. - New support for clock skew/delay generic DT bindings and generic pin config options for this. - Minor documentation improvements. Various: - The Renesas SH-PFC pin controller has evolved a lot. It seems Renesas are churning out new SoCs by the minute. - A bunch of non-critical fixes for the Rockchip driver. - Improve the use of library functions instead of open coding. - Support the MCP28018 variant in the MCP28x08 driver. - Static constifying. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJaDV9TAAoJEEEQszewGV1zf0AQAIlHxM8B0mJPOFv7WdPIHs8j GSGAPv0rPobdgZI8vegosIQmAiry5jjaHP6VGOrK5n8FRxfBLd89NLT7dgK7J9Yx tYcQRQn1/MqZKaIjWWgTes3okEr9s77Of3aWkA9gyvBjTGoo2hu8BTwZOYuPrIPP aYcI7VR0VbTe7FQR1QRtKBXnBTXfznF1j5ckKNY4ahgIPcUgxyh6EA1E61rDorLK gvwwzoBqIKQAcnapgarF7YOJjoE0i7ZoSlhL0b0nvhcgolyK/zLN4xujLcTGPeTJ hQwe7LhxtvtmJmu0jRMuetDLFT52d6eq8ttyFBMULkgRzcgMv6GZZXUy4k92t7ZT F2DRbAjyAlxkhUhQ8BORzEXwfWYITt1M49jWQqugdDR2fV/MAlF8motOkVBl73iS zHIQ/ZDcAD+PlwTHiDyDOUxj7qyDs2MkTLTzfXc0koOQZOqskDHQ1dIf3UzLzZ9S /dx339/ejwP73E0lzOsanhianfonqWZ3Apn3aRG18uqCt2+eHySWpxyRANuOlBZI czERg+47wDfng24xyuH0EElgbS5G0Bt1lT5zLVLdFEvoLmcBHVKqaCkiuvYXOjVM GyMRvQPiJbhT6qiJ+aSP8t/utl1aUhXQLtrUnXxu8qv9tQ6jgmqiQd9855Uvrzb0 ZR2wyNc2jtWzwCfrkWjt =kj/b -----END PGP SIGNATURE----- Merge tag 'pinctrl-v4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.15 kernel cycle: Core: - The pin control Kconfig entry PINCTRL is now turned into a menuconfig option. This obviously has the implication of making the subsystem menu visible in menuconfig. This is happening because of two things: (a) Intel have started to deploy and depend on pin controllers in a way that is affecting users directly. This happens on the highly integrated laptop chipsets named after geographical places: baytrail, broxton, cannonlake, cedarfork, cherryview, denverton, geminilake, lewisburg, merrifield, sunrisepoint... It started a while back and now it is ever more evident that this is crucial infrastructure for x86 laptops and not an embedded obscurity anymore. Users need to be aware. (b) Pin control expanders on I2C and SPI that are arch-agnostic. Currently Semtech SX150X and Microchip MCP28x08 but more are expected. Users will have to be able to configure these in directly for their set-up. - Just go and select GPIOLIB now that we made sure that GPIOLIB is a very vanilla subsystem. Do not depend on it, if we need it, select it. - Exposing the pin control subsystem in menuconfig uncovered a bunch of obscure bugs that are now hopefully fixed, all more or less pertaining to Blackfin. - Unified namespace for cross-calls between pin control and GPIO. - New support for clock skew/delay generic DT bindings and generic pin config options for this. - Minor documentation improvements. Various: - The Renesas SH-PFC pin controller has evolved a lot. It seems Renesas are churning out new SoCs by the minute. - A bunch of non-critical fixes for the Rockchip driver. - Improve the use of library functions instead of open coding. - Support the MCP28018 variant in the MCP28x08 driver. - Static constifying" * tag 'pinctrl-v4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (91 commits) pinctrl: gemini: Fix missing pad descriptions pinctrl: Add some depends on HAS_IOMEM pinctrl: samsung/s3c24xx: add CONFIG_OF dependency pinctrl: gemini: Fix GMAC groups pinctrl: qcom: spmi-gpio: Add pmi8994 gpio support pinctrl: ti-iodelay: remove redundant unused variable dev pinctrl: max77620: Use common error handling code in max77620_pinconf_set() pinctrl: gemini: Implement clock skew/delay config pinctrl: gemini: Use generic DT parser pinctrl: Add skew-delay pin config and bindings pinctrl: armada-37xx: Add edge both type gpio irq support pinctrl: uniphier: remove eMMC hardware reset pin-mux pinctrl: rockchip: Add iomux-route switching support for rk3288 pinctrl: intel: Add Intel Cedar Fork PCH pin controller support pinctrl: intel: Make offset to interrupt status register configurable pinctrl: sunxi: Enforce the strict mode by default pinctrl: sunxi: Disable strict mode for old pinctrl drivers pinctrl: sunxi: Introduce the strict flag pinctrl: sh-pfc: Save/restore registers for PSCI system suspend pinctrl: sh-pfc: r8a7796: Use generic IOCTRL register description ...
379 lines
9.4 KiB
Text
379 lines
9.4 KiB
Text
#
|
|
# PINCTRL infrastructure and drivers
|
|
#
|
|
|
|
menuconfig PINCTRL
|
|
bool "Pin controllers"
|
|
|
|
if PINCTRL
|
|
|
|
config GENERIC_PINCTRL_GROUPS
|
|
bool
|
|
|
|
config PINMUX
|
|
bool "Support pin multiplexing controllers" if COMPILE_TEST
|
|
|
|
config GENERIC_PINMUX_FUNCTIONS
|
|
bool
|
|
select PINMUX
|
|
|
|
config PINCONF
|
|
bool "Support pin configuration controllers" if COMPILE_TEST
|
|
|
|
config GENERIC_PINCONF
|
|
bool
|
|
select PINCONF
|
|
|
|
config DEBUG_PINCTRL
|
|
bool "Debug PINCTRL calls"
|
|
depends on DEBUG_KERNEL
|
|
help
|
|
Say Y here to add some extra checks and diagnostics to PINCTRL calls.
|
|
|
|
config PINCTRL_ADI2
|
|
bool "ADI pin controller driver"
|
|
depends on (BF54x || BF60x)
|
|
depends on !GPIO_ADI
|
|
select PINMUX
|
|
select IRQ_DOMAIN
|
|
help
|
|
This is the pin controller and gpio driver for ADI BF54x, BF60x and
|
|
future processors. This option is selected automatically when specific
|
|
machine and arch are selected to build.
|
|
|
|
config PINCTRL_ARTPEC6
|
|
bool "Axis ARTPEC-6 pin controller driver"
|
|
depends on MACH_ARTPEC6
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
help
|
|
This is the driver for the Axis ARTPEC-6 pin controller. This driver
|
|
supports pin function multiplexing as well as pin bias and drive
|
|
strength configuration. Device tree integration instructions can be
|
|
found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
|
|
|
|
config PINCTRL_AS3722
|
|
tristate "Pinctrl and GPIO driver for ams AS3722 PMIC"
|
|
depends on MFD_AS3722 && GPIOLIB
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
help
|
|
AS3722 device supports the configuration of GPIO pins for different
|
|
functionality. This driver supports the pinmux, push-pull and
|
|
open drain configuration for the GPIO pins of AS3722 devices. It also
|
|
supports the GPIO functionality through gpiolib.
|
|
|
|
config PINCTRL_BF54x
|
|
def_bool y if BF54x
|
|
select PINCTRL_ADI2
|
|
|
|
config PINCTRL_BF60x
|
|
def_bool y if BF60x
|
|
select PINCTRL_ADI2
|
|
|
|
config PINCTRL_AT91
|
|
bool "AT91 pinctrl driver"
|
|
depends on OF
|
|
depends on ARCH_AT91
|
|
select PINMUX
|
|
select PINCONF
|
|
select GPIOLIB
|
|
select OF_GPIO
|
|
select GPIOLIB_IRQCHIP
|
|
help
|
|
Say Y here to enable the at91 pinctrl driver
|
|
|
|
config PINCTRL_AT91PIO4
|
|
bool "AT91 PIO4 pinctrl driver"
|
|
depends on OF
|
|
depends on ARCH_AT91
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
select GPIOLIB
|
|
select GPIOLIB_IRQCHIP
|
|
select OF_GPIO
|
|
help
|
|
Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4
|
|
controller available on sama5d2 SoC.
|
|
|
|
config PINCTRL_AMD
|
|
tristate "AMD GPIO pin control"
|
|
depends on HAS_IOMEM
|
|
select GPIOLIB
|
|
select GPIOLIB_IRQCHIP
|
|
select PINMUX
|
|
select PINCONF
|
|
select GENERIC_PINCONF
|
|
help
|
|
driver for memory mapped GPIO functionality on AMD platforms
|
|
(x86 or arm).Most pins are usually muxed to some other
|
|
functionality by firmware,so only a small amount is available
|
|
for gpio use.
|
|
|
|
Requires ACPI/FDT device enumeration code to set up a platform
|
|
device.
|
|
|
|
config PINCTRL_DA850_PUPD
|
|
tristate "TI DA850/OMAP-L138/AM18XX pullup/pulldown groups"
|
|
depends on OF && (ARCH_DAVINCI_DA850 || COMPILE_TEST)
|
|
select PINCONF
|
|
select GENERIC_PINCONF
|
|
help
|
|
Driver for TI DA850/OMAP-L138/AM18XX pinconf. Used to control
|
|
pullup/pulldown pin groups.
|
|
|
|
config PINCTRL_DIGICOLOR
|
|
bool
|
|
depends on OF && (ARCH_DIGICOLOR || COMPILE_TEST)
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
|
|
config PINCTRL_LANTIQ
|
|
bool
|
|
depends on LANTIQ
|
|
select PINMUX
|
|
select PINCONF
|
|
|
|
config PINCTRL_LPC18XX
|
|
bool "NXP LPC18XX/43XX SCU pinctrl driver"
|
|
depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
|
|
default ARCH_LPC18XX
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
help
|
|
Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU).
|
|
|
|
config PINCTRL_FALCON
|
|
bool
|
|
depends on SOC_FALCON
|
|
depends on PINCTRL_LANTIQ
|
|
|
|
config PINCTRL_GEMINI
|
|
bool
|
|
depends on ARCH_GEMINI
|
|
default ARCH_GEMINI
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
select MFD_SYSCON
|
|
|
|
config PINCTRL_MCP23S08
|
|
tristate "Microchip MCP23xxx I/O expander"
|
|
depends on SPI_MASTER || I2C
|
|
depends on I2C || I2C=n
|
|
select GPIOLIB
|
|
select GPIOLIB_IRQCHIP
|
|
select REGMAP_I2C if I2C
|
|
select REGMAP_SPI if SPI_MASTER
|
|
select GENERIC_PINCONF
|
|
help
|
|
SPI/I2C driver for Microchip MCP23S08/MCP23S17/MCP23008/MCP23017
|
|
I/O expanders.
|
|
This provides a GPIO interface supporting inputs and outputs.
|
|
The I2C versions of the chips can be used as interrupt-controller.
|
|
|
|
config PINCTRL_OXNAS
|
|
bool
|
|
depends on OF
|
|
select PINMUX
|
|
select PINCONF
|
|
select GENERIC_PINCONF
|
|
select GPIOLIB
|
|
select OF_GPIO
|
|
select GPIOLIB_IRQCHIP
|
|
select MFD_SYSCON
|
|
|
|
config PINCTRL_ROCKCHIP
|
|
bool
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
select GENERIC_IRQ_CHIP
|
|
select MFD_SYSCON
|
|
|
|
config PINCTRL_RZA1
|
|
bool "Renesas RZ/A1 gpio and pinctrl driver"
|
|
depends on OF
|
|
depends on ARCH_R7S72100 || COMPILE_TEST
|
|
select GPIOLIB
|
|
select GENERIC_PINCTRL_GROUPS
|
|
select GENERIC_PINMUX_FUNCTIONS
|
|
select GENERIC_PINCONF
|
|
help
|
|
This selects pinctrl driver for Renesas RZ/A1 platforms.
|
|
|
|
config PINCTRL_SINGLE
|
|
tristate "One-register-per-pin type device tree based pinctrl driver"
|
|
depends on OF
|
|
depends on HAS_IOMEM
|
|
select GENERIC_PINCTRL_GROUPS
|
|
select GENERIC_PINMUX_FUNCTIONS
|
|
select GENERIC_PINCONF
|
|
help
|
|
This selects the device tree based generic pinctrl driver.
|
|
|
|
config PINCTRL_SIRF
|
|
bool "CSR SiRFprimaII pin controller driver"
|
|
depends on ARCH_SIRF
|
|
select PINMUX
|
|
select PINCONF
|
|
select GENERIC_PINCONF
|
|
select GPIOLIB_IRQCHIP
|
|
|
|
config PINCTRL_SX150X
|
|
bool "Semtech SX150x I2C GPIO expander pinctrl driver"
|
|
depends on I2C=y
|
|
select PINMUX
|
|
select PINCONF
|
|
select GENERIC_PINCONF
|
|
select GPIOLIB
|
|
select GPIOLIB_IRQCHIP
|
|
select REGMAP
|
|
help
|
|
Say yes here to provide support for Semtech SX150x-series I2C
|
|
GPIO expanders as pinctrl module.
|
|
Compatible models include:
|
|
- 8 bits: sx1508q, sx1502q
|
|
- 16 bits: sx1509q, sx1506q
|
|
|
|
config PINCTRL_PISTACHIO
|
|
def_bool y if MACH_PISTACHIO
|
|
depends on GPIOLIB
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
select GPIOLIB_IRQCHIP
|
|
select OF_GPIO
|
|
|
|
config PINCTRL_ST
|
|
bool
|
|
depends on OF
|
|
select PINMUX
|
|
select PINCONF
|
|
select GPIOLIB_IRQCHIP
|
|
|
|
config PINCTRL_TZ1090
|
|
bool "Toumaz Xenif TZ1090 pin control driver"
|
|
depends on SOC_TZ1090
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
|
|
config PINCTRL_TZ1090_PDC
|
|
bool "Toumaz Xenif TZ1090 PDC pin control driver"
|
|
depends on SOC_TZ1090
|
|
select PINMUX
|
|
select PINCONF
|
|
|
|
config PINCTRL_U300
|
|
bool "U300 pin controller driver"
|
|
depends on ARCH_U300
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
|
|
config PINCTRL_COH901
|
|
bool "ST-Ericsson U300 COH 901 335/571 GPIO"
|
|
depends on GPIOLIB && ARCH_U300 && PINCTRL_U300
|
|
select GPIOLIB_IRQCHIP
|
|
help
|
|
Say yes here to support GPIO interface on ST-Ericsson U300.
|
|
The names of the two IP block variants supported are
|
|
COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
|
|
ports of 8 GPIO pins each.
|
|
|
|
config PINCTRL_MAX77620
|
|
tristate "MAX77620/MAX20024 Pincontrol support"
|
|
depends on MFD_MAX77620 && OF
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
help
|
|
Say Yes here to enable Pin control support for Maxim PMIC MAX77620.
|
|
This PMIC has 8 GPIO pins that work as GPIO as well as special
|
|
function in alternate mode. This driver also configure push-pull,
|
|
open drain, FPS slots etc.
|
|
|
|
config PINCTRL_PALMAS
|
|
tristate "Pinctrl driver for the PALMAS Series MFD devices"
|
|
depends on OF && MFD_PALMAS
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
help
|
|
Palmas device supports the configuration of pins for different
|
|
functionality. This driver supports the pinmux, push-pull and
|
|
open drain configuration for the Palmas series devices like
|
|
TPS65913, TPS80036 etc.
|
|
|
|
config PINCTRL_PIC32
|
|
bool "Microchip PIC32 pin controller driver"
|
|
depends on OF
|
|
depends on MACH_PIC32
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
select GPIOLIB_IRQCHIP
|
|
select OF_GPIO
|
|
help
|
|
This is the pin controller and gpio driver for Microchip PIC32
|
|
microcontrollers. This option is selected automatically when specific
|
|
machine and arch are selected to build.
|
|
|
|
config PINCTRL_PIC32MZDA
|
|
def_bool y if PIC32MZDA
|
|
select PINCTRL_PIC32
|
|
|
|
config PINCTRL_ZYNQ
|
|
bool "Pinctrl driver for Xilinx Zynq"
|
|
depends on ARCH_ZYNQ
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
help
|
|
This selects the pinctrl driver for Xilinx Zynq.
|
|
|
|
config PINCTRL_INGENIC
|
|
bool "Pinctrl driver for the Ingenic JZ47xx SoCs"
|
|
default y
|
|
depends on OF
|
|
depends on MACH_INGENIC || COMPILE_TEST
|
|
select GENERIC_PINCONF
|
|
select GENERIC_PINCTRL_GROUPS
|
|
select GENERIC_PINMUX_FUNCTIONS
|
|
select REGMAP_MMIO
|
|
|
|
config PINCTRL_RK805
|
|
tristate "Pinctrl and GPIO driver for RK805 PMIC"
|
|
depends on MFD_RK808
|
|
select GPIOLIB
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
help
|
|
This selects the pinctrl driver for RK805.
|
|
|
|
source "drivers/pinctrl/aspeed/Kconfig"
|
|
source "drivers/pinctrl/bcm/Kconfig"
|
|
source "drivers/pinctrl/berlin/Kconfig"
|
|
source "drivers/pinctrl/freescale/Kconfig"
|
|
source "drivers/pinctrl/intel/Kconfig"
|
|
source "drivers/pinctrl/mvebu/Kconfig"
|
|
source "drivers/pinctrl/nomadik/Kconfig"
|
|
source "drivers/pinctrl/pxa/Kconfig"
|
|
source "drivers/pinctrl/qcom/Kconfig"
|
|
source "drivers/pinctrl/samsung/Kconfig"
|
|
source "drivers/pinctrl/sh-pfc/Kconfig"
|
|
source "drivers/pinctrl/spear/Kconfig"
|
|
source "drivers/pinctrl/sprd/Kconfig"
|
|
source "drivers/pinctrl/stm32/Kconfig"
|
|
source "drivers/pinctrl/sunxi/Kconfig"
|
|
source "drivers/pinctrl/tegra/Kconfig"
|
|
source "drivers/pinctrl/ti/Kconfig"
|
|
source "drivers/pinctrl/uniphier/Kconfig"
|
|
source "drivers/pinctrl/vt8500/Kconfig"
|
|
source "drivers/pinctrl/mediatek/Kconfig"
|
|
source "drivers/pinctrl/zte/Kconfig"
|
|
source "drivers/pinctrl/meson/Kconfig"
|
|
|
|
config PINCTRL_XWAY
|
|
bool
|
|
depends on SOC_TYPE_XWAY
|
|
depends on PINCTRL_LANTIQ
|
|
|
|
config PINCTRL_TB10X
|
|
bool
|
|
depends on OF && ARC_PLAT_TB10X
|
|
select GPIOLIB
|
|
|
|
endif
|