ea793788f8
The hash used for mapping irq numbers to msi descriptors does not utilize all buckets that were allocated. Fix this by using the same value (computed by the number of bits used for the hash function) at relevant places. Reviewed-by: Gerald Schaefer <gerald.schaefer@de.ibm.com> Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
142 lines
3.2 KiB
C
142 lines
3.2 KiB
C
/*
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* Copyright IBM Corp. 2012
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*
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* Author(s):
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* Jan Glauber <jang@linux.vnet.ibm.com>
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*/
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#define COMPONENT "zPCI"
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#define pr_fmt(fmt) COMPONENT ": " fmt
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/rculist.h>
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#include <linux/hash.h>
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#include <linux/pci.h>
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#include <linux/msi.h>
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#include <asm/hw_irq.h>
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/* mapping of irq numbers to msi_desc */
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static struct hlist_head *msi_hash;
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static const unsigned int msi_hash_bits = 8;
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#define MSI_HASH_BUCKETS (1U << msi_hash_bits)
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#define msi_hashfn(nr) hash_long(nr, msi_hash_bits)
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static DEFINE_SPINLOCK(msi_map_lock);
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struct msi_desc *__irq_get_msi_desc(unsigned int irq)
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{
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struct msi_map *map;
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hlist_for_each_entry_rcu(map,
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&msi_hash[msi_hashfn(irq)], msi_chain)
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if (map->irq == irq)
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return map->msi;
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return NULL;
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}
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int zpci_msi_set_mask_bits(struct msi_desc *msi, u32 mask, u32 flag)
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{
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if (msi->msi_attrib.is_msix) {
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int offset = msi->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_VECTOR_CTRL;
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msi->masked = readl(msi->mask_base + offset);
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writel(flag, msi->mask_base + offset);
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} else {
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if (msi->msi_attrib.maskbit) {
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int pos;
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u32 mask_bits;
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pos = (long) msi->mask_base;
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pci_read_config_dword(msi->dev, pos, &mask_bits);
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mask_bits &= ~(mask);
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mask_bits |= flag & mask;
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pci_write_config_dword(msi->dev, pos, mask_bits);
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} else {
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return 0;
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}
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}
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msi->msi_attrib.maskbit = !!flag;
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return 1;
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}
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int zpci_setup_msi_irq(struct zpci_dev *zdev, struct msi_desc *msi,
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unsigned int nr, int offset)
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{
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struct msi_map *map;
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struct msi_msg msg;
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int rc;
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map = kmalloc(sizeof(*map), GFP_KERNEL);
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if (map == NULL)
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return -ENOMEM;
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map->irq = nr;
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map->msi = msi;
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zdev->msi_map[nr & ZPCI_MSI_MASK] = map;
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INIT_HLIST_NODE(&map->msi_chain);
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pr_debug("%s hashing irq: %u to bucket nr: %llu\n",
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__func__, nr, msi_hashfn(nr));
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hlist_add_head_rcu(&map->msi_chain, &msi_hash[msi_hashfn(nr)]);
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spin_lock(&msi_map_lock);
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rc = irq_set_msi_desc(nr, msi);
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if (rc) {
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spin_unlock(&msi_map_lock);
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hlist_del_rcu(&map->msi_chain);
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kfree(map);
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zdev->msi_map[nr & ZPCI_MSI_MASK] = NULL;
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return rc;
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}
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spin_unlock(&msi_map_lock);
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msg.data = nr - offset;
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msg.address_lo = zdev->msi_addr & 0xffffffff;
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msg.address_hi = zdev->msi_addr >> 32;
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write_msi_msg(nr, &msg);
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return 0;
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}
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void zpci_teardown_msi_irq(struct zpci_dev *zdev, struct msi_desc *msi)
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{
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int irq = msi->irq & ZPCI_MSI_MASK;
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struct msi_map *map;
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msi->msg.address_lo = 0;
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msi->msg.address_hi = 0;
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msi->msg.data = 0;
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msi->irq = 0;
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zpci_msi_set_mask_bits(msi, 1, 1);
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spin_lock(&msi_map_lock);
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map = zdev->msi_map[irq];
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hlist_del_rcu(&map->msi_chain);
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kfree(map);
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zdev->msi_map[irq] = NULL;
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spin_unlock(&msi_map_lock);
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}
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/*
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* The msi hash table has 256 entries which is good for 4..20
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* devices (a typical device allocates 10 + CPUs MSI's). Maybe make
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* the hash table size adjustable later.
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*/
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int __init zpci_msihash_init(void)
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{
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unsigned int i;
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msi_hash = kmalloc(MSI_HASH_BUCKETS * sizeof(*msi_hash), GFP_KERNEL);
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if (!msi_hash)
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return -ENOMEM;
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for (i = 0; i < MSI_HASH_BUCKETS; i++)
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INIT_HLIST_HEAD(&msi_hash[i]);
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return 0;
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}
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void __init zpci_msihash_exit(void)
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{
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kfree(msi_hash);
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}
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