87b868070f
commit 3569dd07aaad71920c5ea4da2d5cc9a167c1ffd4 upstream.
The Intel IOMMU driver opportunistically skips a few top level page
tables from the domain paging directory while programming the IOMMU
context entry. However there is an implicit assumption in the code that
domain's adjusted guest address width (agaw) would always be greater
than IOMMU's agaw.
The IOMMU capabilities in an upcoming platform cause the domain's agaw
to be lower than IOMMU's agaw. The issue is seen when the IOMMU supports
both 4-level and 5-level paging. The domain builds a 4-level page table
based on agaw of 2. However the IOMMU's agaw is set as 3 (5-level). In
this case the code incorrectly tries to skip page page table levels.
This causes the IOMMU driver to avoid programming the context entry. The
fix handles this case and programs the context entry accordingly.
Fixes:
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||
|---|---|---|
| .. | ||
| amd_iommu.c | ||
| amd_iommu_debugfs.c | ||
| amd_iommu_init.c | ||
| amd_iommu_proto.h | ||
| amd_iommu_types.h | ||
| amd_iommu_v2.c | ||
| arm-smmu-regs.h | ||
| arm-smmu-v3.c | ||
| arm-smmu.c | ||
| dma-iommu.c | ||
| dmar.c | ||
| exynos-iommu.c | ||
| fsl_pamu.c | ||
| fsl_pamu.h | ||
| fsl_pamu_domain.c | ||
| fsl_pamu_domain.h | ||
| intel-iommu.c | ||
| intel-pasid.c | ||
| intel-pasid.h | ||
| intel-svm.c | ||
| intel_irq_remapping.c | ||
| io-pgtable-arm-v7s.c | ||
| io-pgtable-arm.c | ||
| io-pgtable.c | ||
| io-pgtable.h | ||
| iommu-debugfs.c | ||
| iommu-sysfs.c | ||
| iommu-traces.c | ||
| iommu.c | ||
| iova.c | ||
| ipmmu-vmsa.c | ||
| irq_remapping.c | ||
| irq_remapping.h | ||
| Kconfig | ||
| Makefile | ||
| msm_iommu.c | ||
| msm_iommu.h | ||
| msm_iommu_hw-8xxx.h | ||
| mtk_iommu.c | ||
| mtk_iommu.h | ||
| mtk_iommu_v1.c | ||
| of_iommu.c | ||
| omap-iommu-debug.c | ||
| omap-iommu.c | ||
| omap-iommu.h | ||
| omap-iopgtable.h | ||
| qcom_iommu.c | ||
| rockchip-iommu.c | ||
| s390-iommu.c | ||
| tegra-gart.c | ||
| tegra-smmu.c | ||