b8b572e101
from include/asm-powerpc. This is the result of a mkdir arch/powerpc/include/asm git mv include/asm-powerpc/* arch/powerpc/include/asm Followed by a few documentation/comment fixups and a couple of places where <asm-powepc/...> was being used explicitly. Of the latter only one was outside the arch code and it is a driver only built for powerpc. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
244 lines
7.6 KiB
C
244 lines
7.6 KiB
C
/*
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* Internal header file for UCC FAST unit routines.
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*
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* Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
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*
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* Authors: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __UCC_FAST_H__
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#define __UCC_FAST_H__
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#include <linux/kernel.h>
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#include <asm/immap_qe.h>
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#include <asm/qe.h>
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#include "ucc.h"
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/* Receive BD's status */
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#define R_E 0x80000000 /* buffer empty */
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#define R_W 0x20000000 /* wrap bit */
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#define R_I 0x10000000 /* interrupt on reception */
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#define R_L 0x08000000 /* last */
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#define R_F 0x04000000 /* first */
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/* transmit BD's status */
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#define T_R 0x80000000 /* ready bit */
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#define T_W 0x20000000 /* wrap bit */
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#define T_I 0x10000000 /* interrupt on completion */
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#define T_L 0x08000000 /* last */
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/* Rx Data buffer must be 4 bytes aligned in most cases */
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#define UCC_FAST_RX_ALIGN 4
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#define UCC_FAST_MRBLR_ALIGNMENT 4
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#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
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/* Sizes */
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#define UCC_FAST_URFS_MIN_VAL 0x88
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#define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR 8
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/* ucc_fast_channel_protocol_mode - UCC FAST mode */
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enum ucc_fast_channel_protocol_mode {
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UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000,
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UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001,
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UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002,
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UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003,
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UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004,
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UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005,
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UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006,
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UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007,
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UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008,
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UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009,
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UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A,
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UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B,
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UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C,
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UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D,
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UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E,
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UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F
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};
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/* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
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enum ucc_fast_transparent_txrx {
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UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000,
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UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000
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};
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/* UCC fast diagnostic mode */
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enum ucc_fast_diag_mode {
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UCC_FAST_DIAGNOSTIC_NORMAL = 0x0,
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UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000,
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UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000,
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UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000
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};
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/* UCC fast Sync length (transparent mode only) */
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enum ucc_fast_sync_len {
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UCC_FAST_SYNC_LEN_NOT_USED = 0x0,
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UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000,
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UCC_FAST_SYNC_LEN_8_BIT = 0x00008000,
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UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000
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};
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/* UCC fast RTS mode */
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enum ucc_fast_ready_to_send {
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UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000,
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UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000
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};
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/* UCC fast receiver decoding mode */
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enum ucc_fast_rx_decoding_method {
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UCC_FAST_RX_ENCODING_NRZ = 0x00000000,
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UCC_FAST_RX_ENCODING_NRZI = 0x00000800,
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UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000,
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UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800
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};
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/* UCC fast transmitter encoding mode */
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enum ucc_fast_tx_encoding_method {
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UCC_FAST_TX_ENCODING_NRZ = 0x00000000,
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UCC_FAST_TX_ENCODING_NRZI = 0x00000100,
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UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200,
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UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300
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};
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/* UCC fast CRC length */
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enum ucc_fast_transparent_tcrc {
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UCC_FAST_16_BIT_CRC = 0x00000000,
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UCC_FAST_CRC_RESERVED0 = 0x00000040,
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UCC_FAST_32_BIT_CRC = 0x00000080,
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UCC_FAST_CRC_RESERVED1 = 0x000000C0
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};
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/* Fast UCC initialization structure */
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struct ucc_fast_info {
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int ucc_num;
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enum qe_clock rx_clock;
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enum qe_clock tx_clock;
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u32 regs;
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int irq;
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u32 uccm_mask;
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int bd_mem_part;
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int brkpt_support;
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int grant_support;
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int tsa;
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int cdp;
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int cds;
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int ctsp;
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int ctss;
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int tci;
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int txsy;
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int rtsm;
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int revd;
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int rsyn;
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u16 max_rx_buf_length;
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u16 urfs;
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u16 urfet;
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u16 urfset;
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u16 utfs;
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u16 utfet;
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u16 utftt;
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u16 ufpt;
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enum ucc_fast_channel_protocol_mode mode;
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enum ucc_fast_transparent_txrx ttx_trx;
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enum ucc_fast_tx_encoding_method tenc;
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enum ucc_fast_rx_decoding_method renc;
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enum ucc_fast_transparent_tcrc tcrc;
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enum ucc_fast_sync_len synl;
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};
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struct ucc_fast_private {
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struct ucc_fast_info *uf_info;
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struct ucc_fast __iomem *uf_regs; /* a pointer to the UCC regs. */
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u32 __iomem *p_ucce; /* a pointer to the event register in memory. */
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u32 __iomem *p_uccm; /* a pointer to the mask register in memory. */
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#ifdef CONFIG_UGETH_TX_ON_DEMAND
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u16 __iomem *p_utodr; /* pointer to the transmit on demand register */
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#endif
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int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
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int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
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int stopped_tx; /* Whether channel has been stopped for Tx
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(STOP_TX, etc.) */
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int stopped_rx; /* Whether channel has been stopped for Rx */
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u32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx
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virtual fifo */
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u32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx
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virtual fifo */
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#ifdef STATISTICS
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u32 tx_frames; /* Transmitted frames counter. */
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u32 rx_frames; /* Received frames counter (only frames
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passed to application). */
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u32 tx_discarded; /* Discarded tx frames counter (frames that
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were discarded by the driver due to errors).
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*/
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u32 rx_discarded; /* Discarded rx frames counter (frames that
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were discarded by the driver due to errors).
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*/
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#endif /* STATISTICS */
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u16 mrblr; /* maximum receive buffer length */
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};
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/* ucc_fast_init
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* Initializes Fast UCC according to user provided parameters.
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*
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* uf_info - (In) pointer to the fast UCC info structure.
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* uccf_ret - (Out) pointer to the fast UCC structure.
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*/
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int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret);
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/* ucc_fast_free
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* Frees all resources for fast UCC.
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*
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* uccf - (In) pointer to the fast UCC structure.
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*/
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void ucc_fast_free(struct ucc_fast_private * uccf);
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/* ucc_fast_enable
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* Enables a fast UCC port.
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* This routine enables Tx and/or Rx through the General UCC Mode Register.
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*
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* uccf - (In) pointer to the fast UCC structure.
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* mode - (In) TX, RX, or both.
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*/
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void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode);
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/* ucc_fast_disable
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* Disables a fast UCC port.
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* This routine disables Tx and/or Rx through the General UCC Mode Register.
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*
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* uccf - (In) pointer to the fast UCC structure.
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* mode - (In) TX, RX, or both.
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*/
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void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode);
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/* ucc_fast_irq
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* Handles interrupts on fast UCC.
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* Called from the general interrupt routine to handle interrupts on fast UCC.
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*
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* uccf - (In) pointer to the fast UCC structure.
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*/
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void ucc_fast_irq(struct ucc_fast_private * uccf);
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/* ucc_fast_transmit_on_demand
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* Immediately forces a poll of the transmitter for data to be sent.
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* Typically, the hardware performs a periodic poll for data that the
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* transmit routine has set up to be transmitted. In cases where
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* this polling cycle is not soon enough, this optional routine can
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* be invoked to force a poll right away, instead. Proper use for
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* each transmission for which this functionality is desired is to
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* call the transmit routine and then this routine right after.
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*
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* uccf - (In) pointer to the fast UCC structure.
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*/
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void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf);
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u32 ucc_fast_get_qe_cr_subblock(int uccf_num);
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void ucc_fast_dump_regs(struct ucc_fast_private * uccf);
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#endif /* __UCC_FAST_H__ */
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