97dcb82de6
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
126 lines
4.4 KiB
C
126 lines
4.4 KiB
C
/*
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* Miscellaneous definitions used to initialise the interrupt vector table
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* with the machine-specific interrupt routines.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1997 by Paul M. Antoine.
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* reworked 1998 by Harald Koerfgen.
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* Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki
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*/
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#ifndef __ASM_DEC_INTERRUPTS_H
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#define __ASM_DEC_INTERRUPTS_H
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#include <irq.h>
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#include <asm/mipsregs.h>
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/*
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* The list of possible system devices which provide an
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* interrupt. Not all devices exist on a given system.
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*/
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#define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */
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/* Ordinary interrupts */
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#define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */
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#define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */
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#define DEC_IRQ_DZ11 3 /* DZ11 (DC7085) serial */
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#define DEC_IRQ_ASC 4 /* ASC (NCR53C94) SCSI */
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#define DEC_IRQ_FLOPPY 5 /* 82077 FDC */
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#define DEC_IRQ_FPU 6 /* R3k FPU */
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#define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */
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#define DEC_IRQ_ISDN 8 /* Am79C30A ISDN */
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#define DEC_IRQ_LANCE 9 /* LANCE (Am7990) Ethernet */
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#define DEC_IRQ_BUS 10 /* memory, I/O bus read/write errors */
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#define DEC_IRQ_PSU 11 /* power supply unit warning */
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#define DEC_IRQ_RTC 12 /* DS1287 RTC */
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#define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */
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#define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */
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#define DEC_IRQ_SII 15 /* SII (DC7061) SCSI */
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#define DEC_IRQ_TC0 16 /* TURBOchannel slot #0 */
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#define DEC_IRQ_TC1 17 /* TURBOchannel slot #1 */
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#define DEC_IRQ_TC2 18 /* TURBOchannel slot #2 */
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#define DEC_IRQ_TIMER 19 /* ARC periodic timer */
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#define DEC_IRQ_VIDEO 20 /* framebuffer */
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/* I/O ASIC DMA interrupts */
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#define DEC_IRQ_ASC_MERR 21 /* ASC memory read error */
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#define DEC_IRQ_ASC_ERR 22 /* ASC page overrun */
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#define DEC_IRQ_ASC_DMA 23 /* ASC buffer pointer loaded */
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#define DEC_IRQ_FLOPPY_ERR 24 /* FDC error */
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#define DEC_IRQ_ISDN_ERR 25 /* ISDN memory read/overrun error */
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#define DEC_IRQ_ISDN_RXDMA 26 /* ISDN recv buffer pointer loaded */
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#define DEC_IRQ_ISDN_TXDMA 27 /* ISDN xmit buffer pointer loaded */
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#define DEC_IRQ_LANCE_MERR 28 /* LANCE memory read error */
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#define DEC_IRQ_SCC0A_RXERR 29 /* SCC0A (printer) receive overrun */
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#define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */
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#define DEC_IRQ_SCC0A_TXERR 31 /* SCC0A xmit memory read/overrun */
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#define DEC_IRQ_SCC0A_TXDMA 32 /* SCC0A transmit page end */
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#define DEC_IRQ_AB_RXERR 33 /* ACCESS.bus receive overrun */
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#define DEC_IRQ_AB_RXDMA 34 /* ACCESS.bus receive half page */
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#define DEC_IRQ_AB_TXERR 35 /* ACCESS.bus xmit memory read/ovrn */
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#define DEC_IRQ_AB_TXDMA 36 /* ACCESS.bus transmit page end */
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#define DEC_IRQ_SCC1A_RXERR 37 /* SCC1A (modem) receive overrun */
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#define DEC_IRQ_SCC1A_RXDMA 38 /* SCC1A receive half page */
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#define DEC_IRQ_SCC1A_TXERR 39 /* SCC1A xmit memory read/overrun */
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#define DEC_IRQ_SCC1A_TXDMA 40 /* SCC1A transmit page end */
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/* TC5 & TC6 are virtual slots for KN02's onboard devices */
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#define DEC_IRQ_TC5 DEC_IRQ_ASC /* virtual PMAZ-AA */
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#define DEC_IRQ_TC6 DEC_IRQ_LANCE /* virtual PMAD-AA */
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#define DEC_NR_INTS 41
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/* Largest of cpu mask_nr tables. */
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#define DEC_MAX_CPU_INTS 6
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/* Largest of asic mask_nr tables. */
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#define DEC_MAX_ASIC_INTS 9
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/*
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* CPU interrupt bits common to all systems.
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*/
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#define DEC_CPU_INR_FPU 7 /* R3k FPU */
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#define DEC_CPU_INR_SW1 1 /* software #1 */
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#define DEC_CPU_INR_SW0 0 /* software #0 */
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#define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */
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#define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE)
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#define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP))
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#define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP)
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#ifndef __ASSEMBLY__
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/*
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* Interrupt table structures to hide differences between systems.
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*/
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typedef union { int i; void *p; } int_ptr;
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extern int dec_interrupt[DEC_NR_INTS];
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extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2];
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extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2];
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extern int cpu_fpu_mask;
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/*
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* Common interrupt routine prototypes for all DECStations
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*/
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extern void kn02_io_int(void);
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extern void kn02xa_io_int(void);
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extern void kn03_io_int(void);
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extern void asic_dma_int(void);
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extern void asic_all_int(void);
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extern void kn02_all_int(void);
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extern void cpu_all_int(void);
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extern void dec_intr_unimplemented(void);
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extern void asic_intr_unimplemented(void);
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#endif /* __ASSEMBLY__ */
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#endif
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