29cb3cd208
There are SoCs where attempting to enter a low power state is ignored, and the CPU continues executing instructions with all state preserved. It is over-complex at that point to disable the MMU just to call the resume path. Instead, allow the suspend finisher to return error codes to abort suspend in this circumstance, where the cpu_suspend internals will then unwind the saved state on the stack. Also omit the tlb flush as no changes to the page tables will have happened. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
127 lines
2.6 KiB
C
127 lines
2.6 KiB
C
/*
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* SA1100 Power Management Routines
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*
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* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License.
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*
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* History:
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*
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* 2001-02-06: Cliff Brake Initial code
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*
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* 2001-02-25: Sukjae Cho <sjcho@east.isi.edu> &
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* Chester Kuo <chester@linux.org.tw>
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* Save more value for the resume function! Support
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* Bitsy/Assabet/Freebird board
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*
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* 2001-08-29: Nicolas Pitre <nico@fluxnic.net>
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* Cleaned up, pushed platform dependent stuff
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* in the platform specific files.
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*
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* 2002-05-27: Nicolas Pitre Killed sleep.h and the kmalloced save array.
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* Storage is local on the stack now.
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/errno.h>
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#include <linux/time.h>
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#include <mach/hardware.h>
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#include <asm/memory.h>
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#include <asm/suspend.h>
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#include <asm/system.h>
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#include <asm/mach/time.h>
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extern int sa1100_finish_suspend(unsigned long);
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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/*
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* List of global SA11x0 peripheral registers to preserve.
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* More ones like CP and general purpose register values are preserved
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* on the stack and then the stack pointer is stored last in sleep.S.
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*/
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enum { SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR,
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SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR,
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SLEEP_SAVE_Ser1SDCR0,
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SLEEP_SAVE_COUNT
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};
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static int sa11x0_pm_enter(suspend_state_t state)
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{
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unsigned long gpio, sleep_save[SLEEP_SAVE_COUNT];
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gpio = GPLR;
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/* save vital registers */
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SAVE(GPDR);
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SAVE(GAFR);
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SAVE(PPDR);
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SAVE(PPSR);
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SAVE(PPAR);
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SAVE(PSDR);
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SAVE(Ser1SDCR0);
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/* Clear previous reset status */
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RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
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/* set resume return address */
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PSPR = virt_to_phys(cpu_resume);
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/* go zzz */
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cpu_suspend(0, sa1100_finish_suspend);
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/*
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* Ensure not to come back here if it wasn't intended
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*/
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PSPR = 0;
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/*
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* Ensure interrupt sources are disabled; we will re-init
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* the interrupt subsystem via the device manager.
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*/
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ICLR = 0;
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ICCR = 1;
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ICMR = 0;
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/* restore registers */
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RESTORE(GPDR);
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RESTORE(GAFR);
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RESTORE(PPDR);
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RESTORE(PPSR);
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RESTORE(PPAR);
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RESTORE(PSDR);
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RESTORE(Ser1SDCR0);
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GPSR = gpio;
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GPCR = ~gpio;
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/*
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* Clear the peripheral sleep-hold bit.
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*/
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PSSR = PSSR_PH;
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return 0;
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}
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static const struct platform_suspend_ops sa11x0_pm_ops = {
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.enter = sa11x0_pm_enter,
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.valid = suspend_valid_only_mem,
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};
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static int __init sa11x0_pm_init(void)
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{
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suspend_set_ops(&sa11x0_pm_ops);
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return 0;
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}
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late_initcall(sa11x0_pm_init);
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