ca5cd877ae
Don't undef __i386__/__x86_64__ in uml anymore, make sure that (few) places that required adjusting the ifdefs got those. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
142 lines
3.8 KiB
C
142 lines
3.8 KiB
C
/* -*- linux-c -*- ------------------------------------------------------- *
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*
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* Copyright 2002 H. Peter Anvin - All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, Inc., 53 Temple Place Ste 330,
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* Bostom MA 02111-1307, USA; either version 2 of the License, or
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* (at your option) any later version; incorporated herein by reference.
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*
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* ----------------------------------------------------------------------- */
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/*
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* raid6mmx.c
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*
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* MMX implementation of RAID-6 syndrome functions
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*/
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#if defined(__i386__) && !defined(__arch_um__)
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#include "raid6.h"
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#include "raid6x86.h"
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/* Shared with raid6sse1.c */
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const struct raid6_mmx_constants {
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u64 x1d;
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} raid6_mmx_constants = {
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0x1d1d1d1d1d1d1d1dULL,
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};
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static int raid6_have_mmx(void)
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{
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/* Not really "boot_cpu" but "all_cpus" */
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return boot_cpu_has(X86_FEATURE_MMX);
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}
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/*
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* Plain MMX implementation
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*/
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static void raid6_mmx1_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d));
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asm volatile("pxor %mm5,%mm5"); /* Zero temp */
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for ( d = 0 ; d < bytes ; d += 8 ) {
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asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d])); /* P[0] */
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asm volatile("movq %mm2,%mm4"); /* Q[0] */
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for ( z = z0-1 ; z >= 0 ; z-- ) {
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asm volatile("movq %0,%%mm6" : : "m" (dptr[z][d]));
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asm volatile("pcmpgtb %mm4,%mm5");
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asm volatile("paddb %mm4,%mm4");
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asm volatile("pand %mm0,%mm5");
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asm volatile("pxor %mm5,%mm4");
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asm volatile("pxor %mm5,%mm5");
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asm volatile("pxor %mm6,%mm2");
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asm volatile("pxor %mm6,%mm4");
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}
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asm volatile("movq %%mm2,%0" : "=m" (p[d]));
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asm volatile("pxor %mm2,%mm2");
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asm volatile("movq %%mm4,%0" : "=m" (q[d]));
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asm volatile("pxor %mm4,%mm4");
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}
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_mmxx1 = {
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raid6_mmx1_gen_syndrome,
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raid6_have_mmx,
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"mmxx1",
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0
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};
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/*
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* Unrolled-by-2 MMX implementation
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*/
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static void raid6_mmx2_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d));
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asm volatile("pxor %mm5,%mm5"); /* Zero temp */
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asm volatile("pxor %mm7,%mm7"); /* Zero temp */
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for ( d = 0 ; d < bytes ; d += 16 ) {
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asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d])); /* P[0] */
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asm volatile("movq %0,%%mm3" : : "m" (dptr[z0][d+8]));
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asm volatile("movq %mm2,%mm4"); /* Q[0] */
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asm volatile("movq %mm3,%mm6"); /* Q[1] */
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for ( z = z0-1 ; z >= 0 ; z-- ) {
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asm volatile("pcmpgtb %mm4,%mm5");
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asm volatile("pcmpgtb %mm6,%mm7");
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asm volatile("paddb %mm4,%mm4");
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asm volatile("paddb %mm6,%mm6");
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asm volatile("pand %mm0,%mm5");
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asm volatile("pand %mm0,%mm7");
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asm volatile("pxor %mm5,%mm4");
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asm volatile("pxor %mm7,%mm6");
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asm volatile("movq %0,%%mm5" : : "m" (dptr[z][d]));
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asm volatile("movq %0,%%mm7" : : "m" (dptr[z][d+8]));
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asm volatile("pxor %mm5,%mm2");
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asm volatile("pxor %mm7,%mm3");
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asm volatile("pxor %mm5,%mm4");
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asm volatile("pxor %mm7,%mm6");
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asm volatile("pxor %mm5,%mm5");
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asm volatile("pxor %mm7,%mm7");
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}
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asm volatile("movq %%mm2,%0" : "=m" (p[d]));
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asm volatile("movq %%mm3,%0" : "=m" (p[d+8]));
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asm volatile("movq %%mm4,%0" : "=m" (q[d]));
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asm volatile("movq %%mm6,%0" : "=m" (q[d+8]));
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}
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_mmxx2 = {
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raid6_mmx2_gen_syndrome,
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raid6_have_mmx,
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"mmxx2",
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0
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};
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#endif
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