f17fddc9e2
The fastrcvint code's purpose was to avoid reading the interrupt status if kernel packets were in the receive queue (to reduce overhead). Because intstatus was not read, we could miss the error interrupt bit indicating freeze mode, since it only delivers a single interrupt, even if still pending after intclear is written. This patch removes that unsafe optimization. Signed-off-by: Dave Olson <dave.olson@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com> |
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| amso1100 | ||
| cxgb3 | ||
| ehca | ||
| ipath | ||
| mlx4 | ||
| mthca | ||