f15cbe6f1a
This follows the sparc changes a439fe51a1.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
64 lines
1.5 KiB
C
64 lines
1.5 KiB
C
/*
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* include/asm-sh/ubc.h
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2002, 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_SH_UBC_H
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#define __ASM_SH_UBC_H
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#ifdef __KERNEL__
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#include <cpu/ubc.h>
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/* User Break Controller */
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
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#define UBC_TYPE_SH7729 (current_cpu_data.type == CPU_SH7729)
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#else
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#define UBC_TYPE_SH7729 0
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#endif
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#define BAMR_ASID (1 << 2)
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#define BAMR_NONE 0
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#define BAMR_10 0x1
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#define BAMR_12 0x2
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#define BAMR_ALL 0x3
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#define BAMR_16 0x8
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#define BAMR_20 0x9
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#define BBR_INST (1 << 4)
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#define BBR_DATA (2 << 4)
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#define BBR_READ (1 << 2)
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#define BBR_WRITE (2 << 2)
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#define BBR_BYTE 0x1
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#define BBR_HALF 0x2
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#define BBR_LONG 0x3
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#define BBR_QUAD (1 << 6) /* SH7750 */
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#define BBR_CPU (1 << 6) /* SH7709A,SH7729 */
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#define BBR_DMA (2 << 6) /* SH7709A,SH7729 */
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#define BRCR_CMFA (1 << 15)
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#define BRCR_CMFB (1 << 14)
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#define BRCR_PCTE (1 << 11)
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#define BRCR_PCBA (1 << 10) /* 1: after execution */
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#define BRCR_DBEB (1 << 7)
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#define BRCR_PCBB (1 << 6)
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#define BRCR_SEQ (1 << 3)
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#define BRCR_UBDE (1 << 0)
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#ifndef __ASSEMBLY__
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/* arch/sh/kernel/cpu/ubc.S */
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extern void ubc_sleep(void);
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#ifdef CONFIG_UBC_WAKEUP
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extern void ubc_wakeup(void);
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#else
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#define ubc_wakeup() do { } while (0)
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#endif
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#endif
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_UBC_H */
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