1468 lines
39 KiB
C
1468 lines
39 KiB
C
/*
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* Copyright 2004-2010 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/delay.h>
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#include <linux/console.h>
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#include <linux/bootmem.h>
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#include <linux/seq_file.h>
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#include <linux/cpu.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/tty.h>
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#include <linux/pfn.h>
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#ifdef CONFIG_MTD_UCLINUX
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#include <linux/mtd/map.h>
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#include <linux/ext2_fs.h>
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#include <uapi/linux/cramfs_fs.h>
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#include <linux/romfs_fs.h>
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#endif
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#include <asm/cplb.h>
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#include <asm/cacheflush.h>
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#include <asm/blackfin.h>
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#include <asm/cplbinit.h>
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#include <asm/clocks.h>
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#include <asm/div64.h>
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#include <asm/cpu.h>
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#include <asm/fixed_code.h>
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#include <asm/early_printk.h>
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#include <asm/irq_handler.h>
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#include <asm/pda.h>
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#ifdef CONFIG_BF60x
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#include <mach/pm.h>
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#endif
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#ifdef CONFIG_SCB_PRIORITY
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#include <asm/scb.h>
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#endif
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u16 _bfin_swrst;
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EXPORT_SYMBOL(_bfin_swrst);
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unsigned long memory_start, memory_end, physical_mem_end;
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unsigned long _rambase, _ramstart, _ramend;
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unsigned long reserved_mem_dcache_on;
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unsigned long reserved_mem_icache_on;
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EXPORT_SYMBOL(memory_start);
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EXPORT_SYMBOL(memory_end);
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EXPORT_SYMBOL(physical_mem_end);
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EXPORT_SYMBOL(_ramend);
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EXPORT_SYMBOL(reserved_mem_dcache_on);
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#ifdef CONFIG_MTD_UCLINUX
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extern struct map_info uclinux_ram_map;
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unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
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EXPORT_SYMBOL(memory_mtd_end);
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EXPORT_SYMBOL(memory_mtd_start);
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EXPORT_SYMBOL(mtd_size);
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#endif
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char __initdata command_line[COMMAND_LINE_SIZE];
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struct blackfin_initial_pda __initdata initial_pda;
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/* boot memmap, for parsing "memmap=" */
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#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
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#define BFIN_MEMMAP_RAM 1
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#define BFIN_MEMMAP_RESERVED 2
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static struct bfin_memmap {
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int nr_map;
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struct bfin_memmap_entry {
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unsigned long long addr; /* start of memory segment */
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unsigned long long size;
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unsigned long type;
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} map[BFIN_MEMMAP_MAX];
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} bfin_memmap __initdata;
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/* for memmap sanitization */
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struct change_member {
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struct bfin_memmap_entry *pentry; /* pointer to original entry */
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unsigned long long addr; /* address for this change point */
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};
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static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
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static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
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static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
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static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
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DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data);
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static int early_init_clkin_hz(char *buf);
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#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
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void __init generate_cplb_tables(void)
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{
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unsigned int cpu;
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generate_cplb_tables_all();
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/* Generate per-CPU I&D CPLB tables */
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for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
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generate_cplb_tables_cpu(cpu);
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}
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#endif
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void bfin_setup_caches(unsigned int cpu)
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{
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#ifdef CONFIG_BFIN_ICACHE
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bfin_icache_init(icplb_tbl[cpu]);
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#endif
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#ifdef CONFIG_BFIN_DCACHE
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bfin_dcache_init(dcplb_tbl[cpu]);
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#endif
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bfin_setup_cpudata(cpu);
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/*
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* In cache coherence emulation mode, we need to have the
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* D-cache enabled before running any atomic operation which
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* might involve cache invalidation (i.e. spinlock, rwlock).
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* So printk's are deferred until then.
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*/
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#ifdef CONFIG_BFIN_ICACHE
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printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
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printk(KERN_INFO " External memory:"
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# ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
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" cacheable"
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# else
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" uncacheable"
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# endif
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" in instruction cache\n");
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if (L2_LENGTH)
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printk(KERN_INFO " L2 SRAM :"
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# ifdef CONFIG_BFIN_L2_ICACHEABLE
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" cacheable"
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# else
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" uncacheable"
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# endif
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" in instruction cache\n");
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#else
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printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
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#endif
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#ifdef CONFIG_BFIN_DCACHE
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printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
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printk(KERN_INFO " External memory:"
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# if defined CONFIG_BFIN_EXTMEM_WRITEBACK
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" cacheable (write-back)"
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# elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
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" cacheable (write-through)"
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# else
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" uncacheable"
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# endif
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" in data cache\n");
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if (L2_LENGTH)
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printk(KERN_INFO " L2 SRAM :"
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# if defined CONFIG_BFIN_L2_WRITEBACK
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" cacheable (write-back)"
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# elif defined CONFIG_BFIN_L2_WRITETHROUGH
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" cacheable (write-through)"
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# else
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" uncacheable"
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# endif
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" in data cache\n");
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#else
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printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
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#endif
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}
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void bfin_setup_cpudata(unsigned int cpu)
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{
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struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
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cpudata->imemctl = bfin_read_IMEM_CONTROL();
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cpudata->dmemctl = bfin_read_DMEM_CONTROL();
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}
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void __init bfin_cache_init(void)
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{
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#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
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generate_cplb_tables();
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#endif
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bfin_setup_caches(0);
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}
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void __init bfin_relocate_l1_mem(void)
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{
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unsigned long text_l1_len = (unsigned long)_text_l1_len;
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unsigned long data_l1_len = (unsigned long)_data_l1_len;
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unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
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unsigned long l2_len = (unsigned long)_l2_len;
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early_shadow_stamp();
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/*
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* due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S
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* we know that everything about l1 text/data is nice and aligned,
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* so copy by 4 byte chunks, and don't worry about overlapping
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* src/dest.
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*
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* We can't use the dma_memcpy functions, since they can call
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* scheduler functions which might be in L1 :( and core writes
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* into L1 instruction cause bad access errors, so we are stuck,
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* we are required to use DMA, but can't use the common dma
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* functions. We can't use memcpy either - since that might be
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* going to be in the relocated L1
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*/
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blackfin_dma_early_init();
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/* if necessary, copy L1 text to L1 instruction SRAM */
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if (L1_CODE_LENGTH && text_l1_len)
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early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len);
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/* if necessary, copy L1 data to L1 data bank A SRAM */
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if (L1_DATA_A_LENGTH && data_l1_len)
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early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len);
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/* if necessary, copy L1 data B to L1 data bank B SRAM */
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if (L1_DATA_B_LENGTH && data_b_l1_len)
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early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len);
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early_dma_memcpy_done();
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#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
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blackfin_iflush_l1_entry[0] = (unsigned long)blackfin_icache_flush_range_l1;
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#endif
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/* if necessary, copy L2 text/data to L2 SRAM */
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if (L2_LENGTH && l2_len)
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memcpy(_stext_l2, _l2_lma, l2_len);
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}
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#ifdef CONFIG_SMP
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void __init bfin_relocate_coreb_l1_mem(void)
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{
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unsigned long text_l1_len = (unsigned long)_text_l1_len;
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unsigned long data_l1_len = (unsigned long)_data_l1_len;
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unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
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blackfin_dma_early_init();
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/* if necessary, copy L1 text to L1 instruction SRAM */
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if (L1_CODE_LENGTH && text_l1_len)
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early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma,
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text_l1_len);
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/* if necessary, copy L1 data to L1 data bank A SRAM */
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if (L1_DATA_A_LENGTH && data_l1_len)
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early_dma_memcpy((void *)COREB_L1_DATA_A_START, _data_l1_lma,
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data_l1_len);
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/* if necessary, copy L1 data B to L1 data bank B SRAM */
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if (L1_DATA_B_LENGTH && data_b_l1_len)
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early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma,
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data_b_l1_len);
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early_dma_memcpy_done();
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#ifdef CONFIG_ICACHE_FLUSH_L1
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blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 -
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(unsigned long)_stext_l1 + COREB_L1_CODE_START;
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#endif
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}
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#endif
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#ifdef CONFIG_ROMKERNEL
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void __init bfin_relocate_xip_data(void)
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{
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early_shadow_stamp();
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memcpy(_sdata, _data_lma, (unsigned long)_data_len - THREAD_SIZE + sizeof(struct thread_info));
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memcpy(_sinitdata, _init_data_lma, (unsigned long)_init_data_len);
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}
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#endif
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/* add_memory_region to memmap */
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static void __init add_memory_region(unsigned long long start,
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unsigned long long size, int type)
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{
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int i;
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i = bfin_memmap.nr_map;
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if (i == BFIN_MEMMAP_MAX) {
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printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
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return;
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}
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bfin_memmap.map[i].addr = start;
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bfin_memmap.map[i].size = size;
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bfin_memmap.map[i].type = type;
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bfin_memmap.nr_map++;
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}
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/*
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* Sanitize the boot memmap, removing overlaps.
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*/
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static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
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{
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struct change_member *change_tmp;
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unsigned long current_type, last_type;
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unsigned long long last_addr;
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int chgidx, still_changing;
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int overlap_entries;
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int new_entry;
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int old_nr, new_nr, chg_nr;
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int i;
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/*
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Visually we're performing the following (1,2,3,4 = memory types)
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Sample memory map (w/overlaps):
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____22__________________
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______________________4_
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____1111________________
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_44_____________________
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11111111________________
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____________________33__
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___________44___________
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__________33333_________
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______________22________
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___________________2222_
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_________111111111______
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_____________________11_
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_________________4______
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Sanitized equivalent (no overlap):
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1_______________________
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_44_____________________
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___1____________________
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____22__________________
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______11________________
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_________1______________
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__________3_____________
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___________44___________
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_____________33_________
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_______________2________
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________________1_______
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_________________4______
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___________________2____
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____________________33__
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______________________4_
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*/
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/* if there's only one memory region, don't bother */
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if (*pnr_map < 2)
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return -1;
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old_nr = *pnr_map;
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/* bail out if we find any unreasonable addresses in memmap */
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for (i = 0; i < old_nr; i++)
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if (map[i].addr + map[i].size < map[i].addr)
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return -1;
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/* create pointers for initial change-point information (for sorting) */
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for (i = 0; i < 2*old_nr; i++)
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change_point[i] = &change_point_list[i];
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/* record all known change-points (starting and ending addresses),
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omitting those that are for empty memory regions */
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chgidx = 0;
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for (i = 0; i < old_nr; i++) {
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if (map[i].size != 0) {
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change_point[chgidx]->addr = map[i].addr;
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change_point[chgidx++]->pentry = &map[i];
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change_point[chgidx]->addr = map[i].addr + map[i].size;
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change_point[chgidx++]->pentry = &map[i];
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}
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}
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chg_nr = chgidx; /* true number of change-points */
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/* sort change-point list by memory addresses (low -> high) */
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still_changing = 1;
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while (still_changing) {
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still_changing = 0;
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for (i = 1; i < chg_nr; i++) {
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/* if <current_addr> > <last_addr>, swap */
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/* or, if current=<start_addr> & last=<end_addr>, swap */
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if ((change_point[i]->addr < change_point[i-1]->addr) ||
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((change_point[i]->addr == change_point[i-1]->addr) &&
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(change_point[i]->addr == change_point[i]->pentry->addr) &&
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(change_point[i-1]->addr != change_point[i-1]->pentry->addr))
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) {
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change_tmp = change_point[i];
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change_point[i] = change_point[i-1];
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change_point[i-1] = change_tmp;
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still_changing = 1;
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}
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}
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}
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/* create a new memmap, removing overlaps */
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overlap_entries = 0; /* number of entries in the overlap table */
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new_entry = 0; /* index for creating new memmap entries */
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last_type = 0; /* start with undefined memory type */
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last_addr = 0; /* start with 0 as last starting address */
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/* loop through change-points, determining affect on the new memmap */
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for (chgidx = 0; chgidx < chg_nr; chgidx++) {
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/* keep track of all overlapping memmap entries */
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if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
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/* add map entry to overlap list (> 1 entry implies an overlap) */
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overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
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} else {
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/* remove entry from list (order independent, so swap with last) */
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for (i = 0; i < overlap_entries; i++) {
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if (overlap_list[i] == change_point[chgidx]->pentry)
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overlap_list[i] = overlap_list[overlap_entries-1];
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}
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overlap_entries--;
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}
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/* if there are overlapping entries, decide which "type" to use */
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/* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
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current_type = 0;
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for (i = 0; i < overlap_entries; i++)
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if (overlap_list[i]->type > current_type)
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current_type = overlap_list[i]->type;
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/* continue building up new memmap based on this information */
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if (current_type != last_type) {
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if (last_type != 0) {
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new_map[new_entry].size =
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change_point[chgidx]->addr - last_addr;
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/* move forward only if the new size was non-zero */
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if (new_map[new_entry].size != 0)
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if (++new_entry >= BFIN_MEMMAP_MAX)
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break; /* no more space left for new entries */
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}
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if (current_type != 0) {
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new_map[new_entry].addr = change_point[chgidx]->addr;
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new_map[new_entry].type = current_type;
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last_addr = change_point[chgidx]->addr;
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}
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last_type = current_type;
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}
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}
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new_nr = new_entry; /* retain count for new entries */
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/* copy new mapping into original location */
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memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
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*pnr_map = new_nr;
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return 0;
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}
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static void __init print_memory_map(char *who)
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{
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int i;
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for (i = 0; i < bfin_memmap.nr_map; i++) {
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printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
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bfin_memmap.map[i].addr,
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bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
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switch (bfin_memmap.map[i].type) {
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case BFIN_MEMMAP_RAM:
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printk(KERN_CONT "(usable)\n");
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break;
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case BFIN_MEMMAP_RESERVED:
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printk(KERN_CONT "(reserved)\n");
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break;
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default:
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printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type);
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break;
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}
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}
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}
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static __init int parse_memmap(char *arg)
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{
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unsigned long long start_at, mem_size;
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if (!arg)
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return -EINVAL;
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mem_size = memparse(arg, &arg);
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if (*arg == '@') {
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start_at = memparse(arg+1, &arg);
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add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
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} else if (*arg == '$') {
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start_at = memparse(arg+1, &arg);
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add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
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|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Initial parsing of the command line. Currently, we support:
|
|
* - Controlling the linux memory size: mem=xxx[KMG]
|
|
* - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
|
|
* $ -> reserved memory is dcacheable
|
|
* # -> reserved memory is icacheable
|
|
* - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
|
|
* @ from <start> to <start>+<mem>, type RAM
|
|
* $ from <start> to <start>+<mem>, type RESERVED
|
|
*/
|
|
static __init void parse_cmdline_early(char *cmdline_p)
|
|
{
|
|
char c = ' ', *to = cmdline_p;
|
|
unsigned int memsize;
|
|
for (;;) {
|
|
if (c == ' ') {
|
|
if (!memcmp(to, "mem=", 4)) {
|
|
to += 4;
|
|
memsize = memparse(to, &to);
|
|
if (memsize)
|
|
_ramend = memsize;
|
|
|
|
} else if (!memcmp(to, "max_mem=", 8)) {
|
|
to += 8;
|
|
memsize = memparse(to, &to);
|
|
if (memsize) {
|
|
physical_mem_end = memsize;
|
|
if (*to != ' ') {
|
|
if (*to == '$'
|
|
|| *(to + 1) == '$')
|
|
reserved_mem_dcache_on = 1;
|
|
if (*to == '#'
|
|
|| *(to + 1) == '#')
|
|
reserved_mem_icache_on = 1;
|
|
}
|
|
}
|
|
} else if (!memcmp(to, "clkin_hz=", 9)) {
|
|
to += 9;
|
|
early_init_clkin_hz(to);
|
|
#ifdef CONFIG_EARLY_PRINTK
|
|
} else if (!memcmp(to, "earlyprintk=", 12)) {
|
|
to += 12;
|
|
setup_early_printk(to);
|
|
#endif
|
|
} else if (!memcmp(to, "memmap=", 7)) {
|
|
to += 7;
|
|
parse_memmap(to);
|
|
}
|
|
}
|
|
c = *(to++);
|
|
if (!c)
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Setup memory defaults from user config.
|
|
* The physical memory layout looks like:
|
|
*
|
|
* [_rambase, _ramstart]: kernel image
|
|
* [memory_start, memory_end]: dynamic memory managed by kernel
|
|
* [memory_end, _ramend]: reserved memory
|
|
* [memory_mtd_start(memory_end),
|
|
* memory_mtd_start + mtd_size]: rootfs (if any)
|
|
* [_ramend - DMA_UNCACHED_REGION,
|
|
* _ramend]: uncached DMA region
|
|
* [_ramend, physical_mem_end]: memory not managed by kernel
|
|
*/
|
|
static __init void memory_setup(void)
|
|
{
|
|
#ifdef CONFIG_MTD_UCLINUX
|
|
unsigned long mtd_phys = 0;
|
|
#endif
|
|
unsigned long max_mem;
|
|
|
|
_rambase = CONFIG_BOOT_LOAD;
|
|
_ramstart = (unsigned long)_end;
|
|
|
|
if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
|
|
console_init();
|
|
panic("DMA region exceeds memory limit: %lu.",
|
|
_ramend - _ramstart);
|
|
}
|
|
max_mem = memory_end = _ramend - DMA_UNCACHED_REGION;
|
|
|
|
#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
|
|
/* Due to a Hardware Anomaly we need to limit the size of usable
|
|
* instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
|
|
* 05000263 - Hardware loop corrupted when taking an ICPLB exception
|
|
*/
|
|
# if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
|
|
if (max_mem >= 56 * 1024 * 1024)
|
|
max_mem = 56 * 1024 * 1024;
|
|
# else
|
|
if (max_mem >= 60 * 1024 * 1024)
|
|
max_mem = 60 * 1024 * 1024;
|
|
# endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
|
|
#endif /* ANOMALY_05000263 */
|
|
|
|
|
|
#ifdef CONFIG_MPU
|
|
/* Round up to multiple of 4MB */
|
|
memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
|
|
#else
|
|
memory_start = PAGE_ALIGN(_ramstart);
|
|
#endif
|
|
|
|
#if defined(CONFIG_MTD_UCLINUX)
|
|
/* generic memory mapped MTD driver */
|
|
memory_mtd_end = memory_end;
|
|
|
|
mtd_phys = _ramstart;
|
|
mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
|
|
|
|
# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
|
|
if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
|
|
mtd_size =
|
|
PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
|
|
# endif
|
|
|
|
# if defined(CONFIG_CRAMFS)
|
|
if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
|
|
mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
|
|
# endif
|
|
|
|
# if defined(CONFIG_ROMFS_FS)
|
|
if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
|
|
&& ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) {
|
|
mtd_size =
|
|
PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
|
|
|
|
/* ROM_FS is XIP, so if we found it, we need to limit memory */
|
|
if (memory_end > max_mem) {
|
|
pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
|
|
(max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
|
|
memory_end = max_mem;
|
|
}
|
|
}
|
|
# endif /* CONFIG_ROMFS_FS */
|
|
|
|
/* Since the default MTD_UCLINUX has no magic number, we just blindly
|
|
* read 8 past the end of the kernel's image, and look at it.
|
|
* When no image is attached, mtd_size is set to a random number
|
|
* Do some basic sanity checks before operating on things
|
|
*/
|
|
if (mtd_size == 0 || memory_end <= mtd_size) {
|
|
pr_emerg("Could not find valid ram mtd attached.\n");
|
|
} else {
|
|
memory_end -= mtd_size;
|
|
|
|
/* Relocate MTD image to the top of memory after the uncached memory area */
|
|
uclinux_ram_map.phys = memory_mtd_start = memory_end;
|
|
uclinux_ram_map.size = mtd_size;
|
|
pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n",
|
|
_end, mtd_size, (void *)memory_mtd_start);
|
|
dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
|
|
}
|
|
#endif /* CONFIG_MTD_UCLINUX */
|
|
|
|
/* We need lo limit memory, since everything could have a text section
|
|
* of userspace in it, and expose anomaly 05000263. If the anomaly
|
|
* doesn't exist, or we don't need to - then dont.
|
|
*/
|
|
if (memory_end > max_mem) {
|
|
pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
|
|
(max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
|
|
memory_end = max_mem;
|
|
}
|
|
|
|
#ifdef CONFIG_MPU
|
|
#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
|
|
page_mask_nelts = (((_ramend + ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE -
|
|
ASYNC_BANK0_BASE) >> PAGE_SHIFT) + 31) / 32;
|
|
#else
|
|
page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
|
|
#endif
|
|
page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
|
|
#endif
|
|
|
|
init_mm.start_code = (unsigned long)_stext;
|
|
init_mm.end_code = (unsigned long)_etext;
|
|
init_mm.end_data = (unsigned long)_edata;
|
|
init_mm.brk = (unsigned long)0;
|
|
|
|
printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
|
|
printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
|
|
|
|
printk(KERN_INFO "Memory map:\n"
|
|
" fixedcode = 0x%p-0x%p\n"
|
|
" text = 0x%p-0x%p\n"
|
|
" rodata = 0x%p-0x%p\n"
|
|
" bss = 0x%p-0x%p\n"
|
|
" data = 0x%p-0x%p\n"
|
|
" stack = 0x%p-0x%p\n"
|
|
" init = 0x%p-0x%p\n"
|
|
" available = 0x%p-0x%p\n"
|
|
#ifdef CONFIG_MTD_UCLINUX
|
|
" rootfs = 0x%p-0x%p\n"
|
|
#endif
|
|
#if DMA_UNCACHED_REGION > 0
|
|
" DMA Zone = 0x%p-0x%p\n"
|
|
#endif
|
|
, (void *)FIXED_CODE_START, (void *)FIXED_CODE_END,
|
|
_stext, _etext,
|
|
__start_rodata, __end_rodata,
|
|
__bss_start, __bss_stop,
|
|
_sdata, _edata,
|
|
(void *)&init_thread_union,
|
|
(void *)((int)(&init_thread_union) + THREAD_SIZE),
|
|
__init_begin, __init_end,
|
|
(void *)_ramstart, (void *)memory_end
|
|
#ifdef CONFIG_MTD_UCLINUX
|
|
, (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
|
|
#endif
|
|
#if DMA_UNCACHED_REGION > 0
|
|
, (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
|
|
#endif
|
|
);
|
|
}
|
|
|
|
/*
|
|
* Find the lowest, highest page frame number we have available
|
|
*/
|
|
void __init find_min_max_pfn(void)
|
|
{
|
|
int i;
|
|
|
|
max_pfn = 0;
|
|
min_low_pfn = PFN_DOWN(memory_end);
|
|
|
|
for (i = 0; i < bfin_memmap.nr_map; i++) {
|
|
unsigned long start, end;
|
|
/* RAM? */
|
|
if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
|
|
continue;
|
|
start = PFN_UP(bfin_memmap.map[i].addr);
|
|
end = PFN_DOWN(bfin_memmap.map[i].addr +
|
|
bfin_memmap.map[i].size);
|
|
if (start >= end)
|
|
continue;
|
|
if (end > max_pfn)
|
|
max_pfn = end;
|
|
if (start < min_low_pfn)
|
|
min_low_pfn = start;
|
|
}
|
|
}
|
|
|
|
static __init void setup_bootmem_allocator(void)
|
|
{
|
|
int bootmap_size;
|
|
int i;
|
|
unsigned long start_pfn, end_pfn;
|
|
unsigned long curr_pfn, last_pfn, size;
|
|
|
|
/* mark memory between memory_start and memory_end usable */
|
|
add_memory_region(memory_start,
|
|
memory_end - memory_start, BFIN_MEMMAP_RAM);
|
|
/* sanity check for overlap */
|
|
sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
|
|
print_memory_map("boot memmap");
|
|
|
|
/* initialize globals in linux/bootmem.h */
|
|
find_min_max_pfn();
|
|
/* pfn of the last usable page frame */
|
|
if (max_pfn > memory_end >> PAGE_SHIFT)
|
|
max_pfn = memory_end >> PAGE_SHIFT;
|
|
/* pfn of last page frame directly mapped by kernel */
|
|
max_low_pfn = max_pfn;
|
|
/* pfn of the first usable page frame after kernel image*/
|
|
if (min_low_pfn < memory_start >> PAGE_SHIFT)
|
|
min_low_pfn = memory_start >> PAGE_SHIFT;
|
|
start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT;
|
|
end_pfn = memory_end >> PAGE_SHIFT;
|
|
|
|
/*
|
|
* give all the memory to the bootmap allocator, tell it to put the
|
|
* boot mem_map at the start of memory.
|
|
*/
|
|
bootmap_size = init_bootmem_node(NODE_DATA(0),
|
|
memory_start >> PAGE_SHIFT, /* map goes here */
|
|
start_pfn, end_pfn);
|
|
|
|
/* register the memmap regions with the bootmem allocator */
|
|
for (i = 0; i < bfin_memmap.nr_map; i++) {
|
|
/*
|
|
* Reserve usable memory
|
|
*/
|
|
if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
|
|
continue;
|
|
/*
|
|
* We are rounding up the start address of usable memory:
|
|
*/
|
|
curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
|
|
if (curr_pfn >= end_pfn)
|
|
continue;
|
|
/*
|
|
* ... and at the end of the usable range downwards:
|
|
*/
|
|
last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
|
|
bfin_memmap.map[i].size);
|
|
|
|
if (last_pfn > end_pfn)
|
|
last_pfn = end_pfn;
|
|
|
|
/*
|
|
* .. finally, did all the rounding and playing
|
|
* around just make the area go away?
|
|
*/
|
|
if (last_pfn <= curr_pfn)
|
|
continue;
|
|
|
|
size = last_pfn - curr_pfn;
|
|
free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
|
|
}
|
|
|
|
/* reserve memory before memory_start, including bootmap */
|
|
reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS,
|
|
memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS,
|
|
BOOTMEM_DEFAULT);
|
|
}
|
|
|
|
#define EBSZ_TO_MEG(ebsz) \
|
|
({ \
|
|
int meg = 0; \
|
|
switch (ebsz & 0xf) { \
|
|
case 0x1: meg = 16; break; \
|
|
case 0x3: meg = 32; break; \
|
|
case 0x5: meg = 64; break; \
|
|
case 0x7: meg = 128; break; \
|
|
case 0x9: meg = 256; break; \
|
|
case 0xb: meg = 512; break; \
|
|
} \
|
|
meg; \
|
|
})
|
|
static inline int __init get_mem_size(void)
|
|
{
|
|
#if defined(EBIU_SDBCTL)
|
|
# if defined(BF561_FAMILY)
|
|
int ret = 0;
|
|
u32 sdbctl = bfin_read_EBIU_SDBCTL();
|
|
ret += EBSZ_TO_MEG(sdbctl >> 0);
|
|
ret += EBSZ_TO_MEG(sdbctl >> 8);
|
|
ret += EBSZ_TO_MEG(sdbctl >> 16);
|
|
ret += EBSZ_TO_MEG(sdbctl >> 24);
|
|
return ret;
|
|
# else
|
|
return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
|
|
# endif
|
|
#elif defined(EBIU_DDRCTL1)
|
|
u32 ddrctl = bfin_read_EBIU_DDRCTL1();
|
|
int ret = 0;
|
|
switch (ddrctl & 0xc0000) {
|
|
case DEVSZ_64:
|
|
ret = 64 / 8;
|
|
break;
|
|
case DEVSZ_128:
|
|
ret = 128 / 8;
|
|
break;
|
|
case DEVSZ_256:
|
|
ret = 256 / 8;
|
|
break;
|
|
case DEVSZ_512:
|
|
ret = 512 / 8;
|
|
break;
|
|
}
|
|
switch (ddrctl & 0x30000) {
|
|
case DEVWD_4:
|
|
ret *= 2;
|
|
case DEVWD_8:
|
|
ret *= 2;
|
|
case DEVWD_16:
|
|
break;
|
|
}
|
|
if ((ddrctl & 0xc000) == 0x4000)
|
|
ret *= 2;
|
|
return ret;
|
|
#elif defined(CONFIG_BF60x)
|
|
u32 ddrctl = bfin_read_DMC0_CFG();
|
|
int ret;
|
|
switch (ddrctl & 0xf00) {
|
|
case DEVSZ_64:
|
|
ret = 64 / 8;
|
|
break;
|
|
case DEVSZ_128:
|
|
ret = 128 / 8;
|
|
break;
|
|
case DEVSZ_256:
|
|
ret = 256 / 8;
|
|
break;
|
|
case DEVSZ_512:
|
|
ret = 512 / 8;
|
|
break;
|
|
case DEVSZ_1G:
|
|
ret = 1024 / 8;
|
|
break;
|
|
case DEVSZ_2G:
|
|
ret = 2048 / 8;
|
|
break;
|
|
}
|
|
return ret;
|
|
#endif
|
|
BUG();
|
|
}
|
|
|
|
__attribute__((weak))
|
|
void __init native_machine_early_platform_add_devices(void)
|
|
{
|
|
}
|
|
|
|
#ifdef CONFIG_BF60x
|
|
static inline u_long bfin_get_clk(char *name)
|
|
{
|
|
struct clk *clk;
|
|
u_long clk_rate;
|
|
|
|
clk = clk_get(NULL, name);
|
|
if (IS_ERR(clk))
|
|
return 0;
|
|
|
|
clk_rate = clk_get_rate(clk);
|
|
clk_put(clk);
|
|
return clk_rate;
|
|
}
|
|
#endif
|
|
|
|
void __init setup_arch(char **cmdline_p)
|
|
{
|
|
u32 mmr;
|
|
unsigned long sclk, cclk;
|
|
|
|
native_machine_early_platform_add_devices();
|
|
|
|
enable_shadow_console();
|
|
|
|
/* Check to make sure we are running on the right processor */
|
|
mmr = bfin_cpuid();
|
|
if (unlikely(CPUID != bfin_cpuid()))
|
|
printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
|
|
CPU, bfin_cpuid(), bfin_revid());
|
|
|
|
#ifdef CONFIG_DUMMY_CONSOLE
|
|
conswitchp = &dummy_con;
|
|
#endif
|
|
|
|
#if defined(CONFIG_CMDLINE_BOOL)
|
|
strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
|
|
command_line[sizeof(command_line) - 1] = 0;
|
|
#endif
|
|
|
|
/* Keep a copy of command line */
|
|
*cmdline_p = &command_line[0];
|
|
memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
|
|
boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
|
|
|
|
memset(&bfin_memmap, 0, sizeof(bfin_memmap));
|
|
|
|
#ifdef CONFIG_BF60x
|
|
/* Should init clock device before parse command early */
|
|
clk_init();
|
|
#endif
|
|
/* If the user does not specify things on the command line, use
|
|
* what the bootloader set things up as
|
|
*/
|
|
physical_mem_end = 0;
|
|
parse_cmdline_early(&command_line[0]);
|
|
|
|
if (_ramend == 0)
|
|
_ramend = get_mem_size() * 1024 * 1024;
|
|
|
|
if (physical_mem_end == 0)
|
|
physical_mem_end = _ramend;
|
|
|
|
memory_setup();
|
|
|
|
#ifndef CONFIG_BF60x
|
|
/* Initialize Async memory banks */
|
|
bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
|
|
bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
|
|
bfin_write_EBIU_AMGCTL(AMGCTLVAL);
|
|
#ifdef CONFIG_EBIU_MBSCTLVAL
|
|
bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL);
|
|
bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
|
|
bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
|
|
#endif
|
|
#endif
|
|
#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
|
|
bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
|
|
bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
|
|
bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15);
|
|
bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() &
|
|
~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
|
|
#endif
|
|
|
|
cclk = get_cclk();
|
|
sclk = get_sclk();
|
|
|
|
if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
|
|
panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
|
|
|
|
#ifdef BF561_FAMILY
|
|
if (ANOMALY_05000266) {
|
|
bfin_read_IMDMA_D0_IRQ_STATUS();
|
|
bfin_read_IMDMA_D1_IRQ_STATUS();
|
|
}
|
|
#endif
|
|
|
|
mmr = bfin_read_TBUFCTL();
|
|
printk(KERN_INFO "Hardware Trace %s and %sabled\n",
|
|
(mmr & 0x1) ? "active" : "off",
|
|
(mmr & 0x2) ? "en" : "dis");
|
|
#ifndef CONFIG_BF60x
|
|
mmr = bfin_read_SYSCR();
|
|
printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
|
|
|
|
/* Newer parts mirror SWRST bits in SYSCR */
|
|
#if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
|
|
defined(CONFIG_BF538) || defined(CONFIG_BF539)
|
|
_bfin_swrst = bfin_read_SWRST();
|
|
#else
|
|
/* Clear boot mode field */
|
|
_bfin_swrst = mmr & ~0xf;
|
|
#endif
|
|
|
|
#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
|
|
bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
|
|
#endif
|
|
#ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
|
|
bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
|
|
#endif
|
|
|
|
#ifdef CONFIG_SMP
|
|
if (_bfin_swrst & SWRST_DBL_FAULT_A) {
|
|
#else
|
|
if (_bfin_swrst & RESET_DOUBLE) {
|
|
#endif
|
|
printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
|
|
#ifdef CONFIG_DEBUG_DOUBLEFAULT
|
|
/* We assume the crashing kernel, and the current symbol table match */
|
|
printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
|
|
initial_pda.seqstat_doublefault & SEQSTAT_EXCAUSE,
|
|
initial_pda.retx_doublefault);
|
|
printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
|
|
initial_pda.dcplb_doublefault_addr);
|
|
printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
|
|
initial_pda.icplb_doublefault_addr);
|
|
#endif
|
|
printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
|
|
initial_pda.retx);
|
|
} else if (_bfin_swrst & RESET_WDOG)
|
|
printk(KERN_INFO "Recovering from Watchdog event\n");
|
|
else if (_bfin_swrst & RESET_SOFTWARE)
|
|
printk(KERN_NOTICE "Reset caused by Software reset\n");
|
|
#endif
|
|
printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
|
|
if (bfin_compiled_revid() == 0xffff)
|
|
printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
|
|
else if (bfin_compiled_revid() == -1)
|
|
printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
|
|
else
|
|
printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
|
|
|
|
if (likely(CPUID == bfin_cpuid())) {
|
|
if (bfin_revid() != bfin_compiled_revid()) {
|
|
if (bfin_compiled_revid() == -1)
|
|
printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
|
|
bfin_revid());
|
|
else if (bfin_compiled_revid() != 0xffff) {
|
|
printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
|
|
bfin_compiled_revid(), bfin_revid());
|
|
if (bfin_compiled_revid() > bfin_revid())
|
|
panic("Error: you are missing anomaly workarounds for this rev");
|
|
}
|
|
}
|
|
if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
|
|
printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
|
|
CPU, bfin_revid());
|
|
}
|
|
|
|
printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
|
|
|
|
#ifdef CONFIG_BF60x
|
|
printk(KERN_INFO "Processor Speed: %lu MHz core clock, %lu MHz SCLk, %lu MHz SCLK0, %lu MHz SCLK1 and %lu MHz DCLK\n",
|
|
cclk / 1000000, bfin_get_clk("SYSCLK") / 1000000, get_sclk0() / 1000000, get_sclk1() / 1000000, get_dclk() / 1000000);
|
|
#else
|
|
printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
|
|
cclk / 1000000, sclk / 1000000);
|
|
#endif
|
|
|
|
setup_bootmem_allocator();
|
|
|
|
paging_init();
|
|
|
|
/* Copy atomic sequences to their fixed location, and sanity check that
|
|
these locations are the ones that we advertise to userspace. */
|
|
memcpy((void *)FIXED_CODE_START, &fixed_code_start,
|
|
FIXED_CODE_END - FIXED_CODE_START);
|
|
BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
|
|
!= SIGRETURN_STUB - FIXED_CODE_START);
|
|
BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
|
|
!= ATOMIC_XCHG32 - FIXED_CODE_START);
|
|
BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
|
|
!= ATOMIC_CAS32 - FIXED_CODE_START);
|
|
BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
|
|
!= ATOMIC_ADD32 - FIXED_CODE_START);
|
|
BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
|
|
!= ATOMIC_SUB32 - FIXED_CODE_START);
|
|
BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
|
|
!= ATOMIC_IOR32 - FIXED_CODE_START);
|
|
BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
|
|
!= ATOMIC_AND32 - FIXED_CODE_START);
|
|
BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
|
|
!= ATOMIC_XOR32 - FIXED_CODE_START);
|
|
BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
|
|
!= SAFE_USER_INSTRUCTION - FIXED_CODE_START);
|
|
|
|
#ifdef CONFIG_SMP
|
|
platform_init_cpus();
|
|
#endif
|
|
init_exception_vectors();
|
|
bfin_cache_init(); /* Initialize caches for the boot CPU */
|
|
#ifdef CONFIG_SCB_PRIORITY
|
|
init_scb();
|
|
#endif
|
|
}
|
|
|
|
static int __init topology_init(void)
|
|
{
|
|
unsigned int cpu;
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
subsys_initcall(topology_init);
|
|
|
|
/* Get the input clock frequency */
|
|
static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
|
|
#ifndef CONFIG_BF60x
|
|
static u_long get_clkin_hz(void)
|
|
{
|
|
return cached_clkin_hz;
|
|
}
|
|
#endif
|
|
static int __init early_init_clkin_hz(char *buf)
|
|
{
|
|
cached_clkin_hz = simple_strtoul(buf, NULL, 0);
|
|
#ifdef BFIN_KERNEL_CLOCK
|
|
if (cached_clkin_hz != CONFIG_CLKIN_HZ)
|
|
panic("cannot change clkin_hz when reprogramming clocks");
|
|
#endif
|
|
return 1;
|
|
}
|
|
early_param("clkin_hz=", early_init_clkin_hz);
|
|
|
|
#ifndef CONFIG_BF60x
|
|
/* Get the voltage input multiplier */
|
|
static u_long get_vco(void)
|
|
{
|
|
static u_long cached_vco;
|
|
u_long msel, pll_ctl;
|
|
|
|
/* The assumption here is that VCO never changes at runtime.
|
|
* If, someday, we support that, then we'll have to change this.
|
|
*/
|
|
if (cached_vco)
|
|
return cached_vco;
|
|
|
|
pll_ctl = bfin_read_PLL_CTL();
|
|
msel = (pll_ctl >> 9) & 0x3F;
|
|
if (0 == msel)
|
|
msel = 64;
|
|
|
|
cached_vco = get_clkin_hz();
|
|
cached_vco >>= (1 & pll_ctl); /* DF bit */
|
|
cached_vco *= msel;
|
|
return cached_vco;
|
|
}
|
|
#endif
|
|
|
|
/* Get the Core clock */
|
|
u_long get_cclk(void)
|
|
{
|
|
#ifdef CONFIG_BF60x
|
|
return bfin_get_clk("CCLK");
|
|
#else
|
|
static u_long cached_cclk_pll_div, cached_cclk;
|
|
u_long csel, ssel;
|
|
|
|
if (bfin_read_PLL_STAT() & 0x1)
|
|
return get_clkin_hz();
|
|
|
|
ssel = bfin_read_PLL_DIV();
|
|
if (ssel == cached_cclk_pll_div)
|
|
return cached_cclk;
|
|
else
|
|
cached_cclk_pll_div = ssel;
|
|
|
|
csel = ((ssel >> 4) & 0x03);
|
|
ssel &= 0xf;
|
|
if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
|
|
cached_cclk = get_vco() / ssel;
|
|
else
|
|
cached_cclk = get_vco() >> csel;
|
|
return cached_cclk;
|
|
#endif
|
|
}
|
|
EXPORT_SYMBOL(get_cclk);
|
|
|
|
#ifdef CONFIG_BF60x
|
|
/* Get the bf60x clock of SCLK0 domain */
|
|
u_long get_sclk0(void)
|
|
{
|
|
return bfin_get_clk("SCLK0");
|
|
}
|
|
EXPORT_SYMBOL(get_sclk0);
|
|
|
|
/* Get the bf60x clock of SCLK1 domain */
|
|
u_long get_sclk1(void)
|
|
{
|
|
return bfin_get_clk("SCLK1");
|
|
}
|
|
EXPORT_SYMBOL(get_sclk1);
|
|
|
|
/* Get the bf60x DRAM clock */
|
|
u_long get_dclk(void)
|
|
{
|
|
return bfin_get_clk("DCLK");
|
|
}
|
|
EXPORT_SYMBOL(get_dclk);
|
|
#endif
|
|
|
|
/* Get the default system clock */
|
|
u_long get_sclk(void)
|
|
{
|
|
#ifdef CONFIG_BF60x
|
|
return get_sclk0();
|
|
#else
|
|
static u_long cached_sclk;
|
|
u_long ssel;
|
|
|
|
/* The assumption here is that SCLK never changes at runtime.
|
|
* If, someday, we support that, then we'll have to change this.
|
|
*/
|
|
if (cached_sclk)
|
|
return cached_sclk;
|
|
|
|
if (bfin_read_PLL_STAT() & 0x1)
|
|
return get_clkin_hz();
|
|
|
|
ssel = bfin_read_PLL_DIV() & 0xf;
|
|
if (0 == ssel) {
|
|
printk(KERN_WARNING "Invalid System Clock\n");
|
|
ssel = 1;
|
|
}
|
|
|
|
cached_sclk = get_vco() / ssel;
|
|
return cached_sclk;
|
|
#endif
|
|
}
|
|
EXPORT_SYMBOL(get_sclk);
|
|
|
|
unsigned long sclk_to_usecs(unsigned long sclk)
|
|
{
|
|
u64 tmp = USEC_PER_SEC * (u64)sclk;
|
|
do_div(tmp, get_sclk());
|
|
return tmp;
|
|
}
|
|
EXPORT_SYMBOL(sclk_to_usecs);
|
|
|
|
unsigned long usecs_to_sclk(unsigned long usecs)
|
|
{
|
|
u64 tmp = get_sclk() * (u64)usecs;
|
|
do_div(tmp, USEC_PER_SEC);
|
|
return tmp;
|
|
}
|
|
EXPORT_SYMBOL(usecs_to_sclk);
|
|
|
|
/*
|
|
* Get CPU information for use by the procfs.
|
|
*/
|
|
static int show_cpuinfo(struct seq_file *m, void *v)
|
|
{
|
|
char *cpu, *mmu, *fpu, *vendor, *cache;
|
|
uint32_t revid;
|
|
int cpu_num = *(unsigned int *)v;
|
|
u_long sclk, cclk;
|
|
u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0;
|
|
struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num);
|
|
|
|
cpu = CPU;
|
|
mmu = "none";
|
|
fpu = "none";
|
|
revid = bfin_revid();
|
|
|
|
sclk = get_sclk();
|
|
cclk = get_cclk();
|
|
|
|
switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
|
|
case 0xca:
|
|
vendor = "Analog Devices";
|
|
break;
|
|
default:
|
|
vendor = "unknown";
|
|
break;
|
|
}
|
|
|
|
seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor);
|
|
|
|
if (CPUID == bfin_cpuid())
|
|
seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
|
|
else
|
|
seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
|
|
CPUID, bfin_cpuid());
|
|
|
|
seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
|
|
"stepping\t: %d ",
|
|
cpu, cclk/1000000, sclk/1000000,
|
|
#ifdef CONFIG_MPU
|
|
"mpu on",
|
|
#else
|
|
"mpu off",
|
|
#endif
|
|
revid);
|
|
|
|
if (bfin_revid() != bfin_compiled_revid()) {
|
|
if (bfin_compiled_revid() == -1)
|
|
seq_printf(m, "(Compiled for Rev none)");
|
|
else if (bfin_compiled_revid() == 0xffff)
|
|
seq_printf(m, "(Compiled for Rev any)");
|
|
else
|
|
seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
|
|
}
|
|
|
|
seq_printf(m, "\ncpu MHz\t\t: %lu.%06lu/%lu.%06lu\n",
|
|
cclk/1000000, cclk%1000000,
|
|
sclk/1000000, sclk%1000000);
|
|
seq_printf(m, "bogomips\t: %lu.%02lu\n"
|
|
"Calibration\t: %lu loops\n",
|
|
(loops_per_jiffy * HZ) / 500000,
|
|
((loops_per_jiffy * HZ) / 5000) % 100,
|
|
(loops_per_jiffy * HZ));
|
|
|
|
/* Check Cache configutation */
|
|
switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
|
|
case ACACHE_BSRAM:
|
|
cache = "dbank-A/B\t: cache/sram";
|
|
dcache_size = 16;
|
|
dsup_banks = 1;
|
|
break;
|
|
case ACACHE_BCACHE:
|
|
cache = "dbank-A/B\t: cache/cache";
|
|
dcache_size = 32;
|
|
dsup_banks = 2;
|
|
break;
|
|
case ASRAM_BSRAM:
|
|
cache = "dbank-A/B\t: sram/sram";
|
|
dcache_size = 0;
|
|
dsup_banks = 0;
|
|
break;
|
|
default:
|
|
cache = "unknown";
|
|
dcache_size = 0;
|
|
dsup_banks = 0;
|
|
break;
|
|
}
|
|
|
|
/* Is it turned on? */
|
|
if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
|
|
dcache_size = 0;
|
|
|
|
if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB))
|
|
icache_size = 0;
|
|
|
|
seq_printf(m, "cache size\t: %d KB(L1 icache) "
|
|
"%d KB(L1 dcache) %d KB(L2 cache)\n",
|
|
icache_size, dcache_size, 0);
|
|
seq_printf(m, "%s\n", cache);
|
|
seq_printf(m, "external memory\t: "
|
|
#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
|
|
"cacheable"
|
|
#else
|
|
"uncacheable"
|
|
#endif
|
|
" in instruction cache\n");
|
|
seq_printf(m, "external memory\t: "
|
|
#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
|
|
"cacheable (write-back)"
|
|
#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
|
|
"cacheable (write-through)"
|
|
#else
|
|
"uncacheable"
|
|
#endif
|
|
" in data cache\n");
|
|
|
|
if (icache_size)
|
|
seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
|
|
BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
|
|
else
|
|
seq_printf(m, "icache setup\t: off\n");
|
|
|
|
seq_printf(m,
|
|
"dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
|
|
dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
|
|
BFIN_DLINES);
|
|
#ifdef __ARCH_SYNC_CORE_DCACHE
|
|
seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]);
|
|
#endif
|
|
#ifdef __ARCH_SYNC_CORE_ICACHE
|
|
seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]);
|
|
#endif
|
|
|
|
seq_printf(m, "\n");
|
|
|
|
if (cpu_num != num_possible_cpus() - 1)
|
|
return 0;
|
|
|
|
if (L2_LENGTH) {
|
|
seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
|
|
seq_printf(m, "L2 SRAM\t\t: "
|
|
#if defined(CONFIG_BFIN_L2_ICACHEABLE)
|
|
"cacheable"
|
|
#else
|
|
"uncacheable"
|
|
#endif
|
|
" in instruction cache\n");
|
|
seq_printf(m, "L2 SRAM\t\t: "
|
|
#if defined(CONFIG_BFIN_L2_WRITEBACK)
|
|
"cacheable (write-back)"
|
|
#elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
|
|
"cacheable (write-through)"
|
|
#else
|
|
"uncacheable"
|
|
#endif
|
|
" in data cache\n");
|
|
}
|
|
seq_printf(m, "board name\t: %s\n", bfin_board_name);
|
|
seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n",
|
|
physical_mem_end >> 10, 0ul, physical_mem_end);
|
|
seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n",
|
|
((int)memory_end - (int)_rambase) >> 10,
|
|
_rambase, memory_end);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void *c_start(struct seq_file *m, loff_t *pos)
|
|
{
|
|
if (*pos == 0)
|
|
*pos = cpumask_first(cpu_online_mask);
|
|
if (*pos >= num_online_cpus())
|
|
return NULL;
|
|
|
|
return pos;
|
|
}
|
|
|
|
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
|
|
{
|
|
*pos = cpumask_next(*pos, cpu_online_mask);
|
|
|
|
return c_start(m, pos);
|
|
}
|
|
|
|
static void c_stop(struct seq_file *m, void *v)
|
|
{
|
|
}
|
|
|
|
const struct seq_operations cpuinfo_op = {
|
|
.start = c_start,
|
|
.next = c_next,
|
|
.stop = c_stop,
|
|
.show = show_cpuinfo,
|
|
};
|
|
|
|
void __init cmdline_init(const char *r0)
|
|
{
|
|
early_shadow_stamp();
|
|
if (r0)
|
|
strncpy(command_line, r0, COMMAND_LINE_SIZE);
|
|
}
|