656 lines
22 KiB
C
656 lines
22 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _MSM_PCM_ROUTING_H
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#define _MSM_PCM_ROUTING_H
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#include <dsp/apr_audio-v2.h>
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#include <dsp/q6adm-v2.h>
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/*
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* These names are used by HAL to specify the BE. If any changes are
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* made to the string names or the max name length corresponding
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* changes need to be made in the HAL to ensure they still match.
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*/
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#define LPASS_BE_NAME_MAX_LENGTH 24
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#define LPASS_BE_PRI_I2S_RX "PRIMARY_I2S_RX"
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#define LPASS_BE_PRI_I2S_TX "PRIMARY_I2S_TX"
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#define LPASS_BE_SLIMBUS_0_RX "SLIMBUS_0_RX"
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#define LPASS_BE_SLIMBUS_0_TX "SLIMBUS_0_TX"
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#define LPASS_BE_HDMI "HDMI"
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#define LPASS_BE_HDMI_MS "HDMI_MS"
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#define LPASS_BE_DISPLAY_PORT "DISPLAY_PORT"
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#define LPASS_BE_DISPLAY_PORT1 "DISPLAY_PORT1"
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#define LPASS_BE_INT_BT_SCO_RX "INT_BT_SCO_RX"
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#define LPASS_BE_INT_BT_SCO_TX "INT_BT_SCO_TX"
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#define LPASS_BE_INT_BT_A2DP_RX "INT_BT_A2DP_RX"
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#define LPASS_BE_INT_FM_RX "INT_FM_RX"
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#define LPASS_BE_INT_FM_TX "INT_FM_TX"
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#define LPASS_BE_AFE_PCM_RX "RT_PROXY_DAI_001_RX"
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#define LPASS_BE_AFE_PCM_TX "RT_PROXY_DAI_002_TX"
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#define LPASS_BE_AUXPCM_RX "AUX_PCM_RX"
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#define LPASS_BE_AUXPCM_TX "AUX_PCM_TX"
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#define LPASS_BE_SEC_AUXPCM_RX "SEC_AUX_PCM_RX"
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#define LPASS_BE_SEC_AUXPCM_TX "SEC_AUX_PCM_TX"
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#define LPASS_BE_TERT_AUXPCM_RX "TERT_AUX_PCM_RX"
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#define LPASS_BE_TERT_AUXPCM_TX "TERT_AUX_PCM_TX"
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#define LPASS_BE_QUAT_AUXPCM_RX "QUAT_AUX_PCM_RX"
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#define LPASS_BE_QUAT_AUXPCM_TX "QUAT_AUX_PCM_TX"
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#define LPASS_BE_QUIN_AUXPCM_RX "QUIN_AUX_PCM_RX"
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#define LPASS_BE_QUIN_AUXPCM_TX "QUIN_AUX_PCM_TX"
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#define LPASS_BE_SEN_AUXPCM_RX "SEN_AUX_PCM_RX"
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#define LPASS_BE_SEN_AUXPCM_TX "SEN_AUX_PCM_TX"
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#define LPASS_BE_VOICE_PLAYBACK_TX "VOICE_PLAYBACK_TX"
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#define LPASS_BE_VOICE2_PLAYBACK_TX "VOICE2_PLAYBACK_TX"
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#define LPASS_BE_INCALL_RECORD_RX "INCALL_RECORD_RX"
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#define LPASS_BE_INCALL_RECORD_TX "INCALL_RECORD_TX"
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#define LPASS_BE_PROXY_RX "PROXY_RX"
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#define LPASS_BE_PROXY_TX "PROXY_TX"
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#define LPASS_BE_SEC_I2S_RX "SECONDARY_I2S_RX"
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#define LPASS_BE_PRI_SPDIF_RX "PRI_SPDIF_RX"
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#define LPASS_BE_PRI_SPDIF_TX "PRI_SPDIF_TX"
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#define LPASS_BE_SEC_SPDIF_RX "SEC_SPDIF_RX"
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#define LPASS_BE_SEC_SPDIF_TX "SEC_SPDIF_TX"
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#define LPASS_BE_MI2S_RX "MI2S_RX"
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#define LPASS_BE_MI2S_TX "MI2S_TX"
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#define LPASS_BE_QUAT_MI2S_RX "QUAT_MI2S_RX"
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#define LPASS_BE_QUAT_MI2S_TX "QUAT_MI2S_TX"
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#define LPASS_BE_SEC_MI2S_RX "SEC_MI2S_RX"
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#define LPASS_BE_SEC_MI2S_RX_SD1 "SEC_MI2S_RX_SD1"
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#define LPASS_BE_SEC_MI2S_TX "SEC_MI2S_TX"
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#define LPASS_BE_PRI_MI2S_RX "PRI_MI2S_RX"
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#define LPASS_BE_PRI_MI2S_TX "PRI_MI2S_TX"
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#define LPASS_BE_TERT_MI2S_RX "TERT_MI2S_RX"
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#define LPASS_BE_TERT_MI2S_TX "TERT_MI2S_TX"
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#define LPASS_BE_AUDIO_I2S_RX "AUDIO_I2S_RX"
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#define LPASS_BE_STUB_RX "STUB_RX"
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#define LPASS_BE_STUB_TX "STUB_TX"
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#define LPASS_BE_SLIMBUS_1_RX "SLIMBUS_1_RX"
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#define LPASS_BE_SLIMBUS_1_TX "SLIMBUS_1_TX"
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#define LPASS_BE_STUB_1_TX "STUB_1_TX"
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#define LPASS_BE_SLIMBUS_2_RX "SLIMBUS_2_RX"
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#define LPASS_BE_SLIMBUS_2_TX "SLIMBUS_2_TX"
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#define LPASS_BE_SLIMBUS_3_RX "SLIMBUS_3_RX"
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#define LPASS_BE_SLIMBUS_3_TX "SLIMBUS_3_TX"
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#define LPASS_BE_SLIMBUS_4_RX "SLIMBUS_4_RX"
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#define LPASS_BE_SLIMBUS_4_TX "SLIMBUS_4_TX"
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#define LPASS_BE_SLIMBUS_TX_VI "SLIMBUS_TX_VI"
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#define LPASS_BE_SLIMBUS_5_RX "SLIMBUS_5_RX"
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#define LPASS_BE_SLIMBUS_5_TX "SLIMBUS_5_TX"
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#define LPASS_BE_SLIMBUS_6_RX "SLIMBUS_6_RX"
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#define LPASS_BE_SLIMBUS_6_TX "SLIMBUS_6_TX"
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#define LPASS_BE_QUIN_MI2S_RX "QUIN_MI2S_RX"
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#define LPASS_BE_QUIN_MI2S_TX "QUIN_MI2S_TX"
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#define LPASS_BE_SENARY_MI2S_TX "SENARY_MI2S_TX"
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#define LPASS_BE_SENARY_MI2S_RX "SENARY_MI2S_RX"
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#define LPASS_BE_PRI_META_MI2S_RX "PRI_META_MI2S_RX"
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#define LPASS_BE_SEC_META_MI2S_RX "SEC_META_MI2S_RX"
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#define LPASS_BE_PRI_TDM_RX_0 "PRI_TDM_RX_0"
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#define LPASS_BE_PRI_TDM_TX_0 "PRI_TDM_TX_0"
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#define LPASS_BE_PRI_TDM_RX_1 "PRI_TDM_RX_1"
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#define LPASS_BE_PRI_TDM_TX_1 "PRI_TDM_TX_1"
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#define LPASS_BE_PRI_TDM_RX_2 "PRI_TDM_RX_2"
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#define LPASS_BE_PRI_TDM_TX_2 "PRI_TDM_TX_2"
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#define LPASS_BE_PRI_TDM_RX_3 "PRI_TDM_RX_3"
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#define LPASS_BE_PRI_TDM_TX_3 "PRI_TDM_TX_3"
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#define LPASS_BE_PRI_TDM_RX_4 "PRI_TDM_RX_4"
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#define LPASS_BE_PRI_TDM_TX_4 "PRI_TDM_TX_4"
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#define LPASS_BE_PRI_TDM_RX_5 "PRI_TDM_RX_5"
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#define LPASS_BE_PRI_TDM_TX_5 "PRI_TDM_TX_5"
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#define LPASS_BE_PRI_TDM_RX_6 "PRI_TDM_RX_6"
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#define LPASS_BE_PRI_TDM_TX_6 "PRI_TDM_TX_6"
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#define LPASS_BE_PRI_TDM_RX_7 "PRI_TDM_RX_7"
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#define LPASS_BE_PRI_TDM_TX_7 "PRI_TDM_TX_7"
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#define LPASS_BE_SEC_TDM_RX_0 "SEC_TDM_RX_0"
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#define LPASS_BE_SEC_TDM_TX_0 "SEC_TDM_TX_0"
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#define LPASS_BE_SEC_TDM_RX_1 "SEC_TDM_RX_1"
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#define LPASS_BE_SEC_TDM_TX_1 "SEC_TDM_TX_1"
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#define LPASS_BE_SEC_TDM_RX_2 "SEC_TDM_RX_2"
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#define LPASS_BE_SEC_TDM_TX_2 "SEC_TDM_TX_2"
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#define LPASS_BE_SEC_TDM_RX_3 "SEC_TDM_RX_3"
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#define LPASS_BE_SEC_TDM_TX_3 "SEC_TDM_TX_3"
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#define LPASS_BE_SEC_TDM_RX_4 "SEC_TDM_RX_4"
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#define LPASS_BE_SEC_TDM_TX_4 "SEC_TDM_TX_4"
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#define LPASS_BE_SEC_TDM_RX_5 "SEC_TDM_RX_5"
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#define LPASS_BE_SEC_TDM_TX_5 "SEC_TDM_TX_5"
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#define LPASS_BE_SEC_TDM_RX_6 "SEC_TDM_RX_6"
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#define LPASS_BE_SEC_TDM_TX_6 "SEC_TDM_TX_6"
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#define LPASS_BE_SEC_TDM_RX_7 "SEC_TDM_RX_7"
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#define LPASS_BE_SEC_TDM_TX_7 "SEC_TDM_TX_7"
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#define LPASS_BE_TERT_TDM_RX_0 "TERT_TDM_RX_0"
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#define LPASS_BE_TERT_TDM_TX_0 "TERT_TDM_TX_0"
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#define LPASS_BE_TERT_TDM_RX_1 "TERT_TDM_RX_1"
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#define LPASS_BE_TERT_TDM_TX_1 "TERT_TDM_TX_1"
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#define LPASS_BE_TERT_TDM_RX_2 "TERT_TDM_RX_2"
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#define LPASS_BE_TERT_TDM_TX_2 "TERT_TDM_TX_2"
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#define LPASS_BE_TERT_TDM_RX_3 "TERT_TDM_RX_3"
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#define LPASS_BE_TERT_TDM_TX_3 "TERT_TDM_TX_3"
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#define LPASS_BE_TERT_TDM_RX_4 "TERT_TDM_RX_4"
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#define LPASS_BE_TERT_TDM_TX_4 "TERT_TDM_TX_4"
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#define LPASS_BE_TERT_TDM_RX_5 "TERT_TDM_RX_5"
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#define LPASS_BE_TERT_TDM_TX_5 "TERT_TDM_TX_5"
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#define LPASS_BE_TERT_TDM_RX_6 "TERT_TDM_RX_6"
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#define LPASS_BE_TERT_TDM_TX_6 "TERT_TDM_TX_6"
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#define LPASS_BE_TERT_TDM_RX_7 "TERT_TDM_RX_7"
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#define LPASS_BE_TERT_TDM_TX_7 "TERT_TDM_TX_7"
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#define LPASS_BE_QUAT_TDM_RX_0 "QUAT_TDM_RX_0"
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#define LPASS_BE_QUAT_TDM_TX_0 "QUAT_TDM_TX_0"
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#define LPASS_BE_QUAT_TDM_RX_1 "QUAT_TDM_RX_1"
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#define LPASS_BE_QUAT_TDM_TX_1 "QUAT_TDM_TX_1"
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#define LPASS_BE_QUAT_TDM_RX_2 "QUAT_TDM_RX_2"
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#define LPASS_BE_QUAT_TDM_TX_2 "QUAT_TDM_TX_2"
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#define LPASS_BE_QUAT_TDM_RX_3 "QUAT_TDM_RX_3"
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#define LPASS_BE_QUAT_TDM_TX_3 "QUAT_TDM_TX_3"
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#define LPASS_BE_QUAT_TDM_RX_4 "QUAT_TDM_RX_4"
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#define LPASS_BE_QUAT_TDM_TX_4 "QUAT_TDM_TX_4"
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#define LPASS_BE_QUAT_TDM_RX_5 "QUAT_TDM_RX_5"
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#define LPASS_BE_QUAT_TDM_TX_5 "QUAT_TDM_TX_5"
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#define LPASS_BE_QUAT_TDM_RX_6 "QUAT_TDM_RX_6"
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#define LPASS_BE_QUAT_TDM_TX_6 "QUAT_TDM_TX_6"
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#define LPASS_BE_QUAT_TDM_RX_7 "QUAT_TDM_RX_7"
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#define LPASS_BE_QUAT_TDM_TX_7 "QUAT_TDM_TX_7"
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#define LPASS_BE_AFE_LOOPBACK_TX "AFE_LOOPBACK_TX"
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#define LPASS_BE_QUIN_TDM_RX_0 "QUIN_TDM_RX_0"
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#define LPASS_BE_QUIN_TDM_TX_0 "QUIN_TDM_TX_0"
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#define LPASS_BE_QUIN_TDM_RX_1 "QUIN_TDM_RX_1"
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#define LPASS_BE_QUIN_TDM_TX_1 "QUIN_TDM_TX_1"
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#define LPASS_BE_QUIN_TDM_RX_2 "QUIN_TDM_RX_2"
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#define LPASS_BE_QUIN_TDM_TX_2 "QUIN_TDM_TX_2"
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#define LPASS_BE_QUIN_TDM_RX_3 "QUIN_TDM_RX_3"
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#define LPASS_BE_QUIN_TDM_TX_3 "QUIN_TDM_TX_3"
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#define LPASS_BE_QUIN_TDM_RX_4 "QUIN_TDM_RX_4"
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#define LPASS_BE_QUIN_TDM_TX_4 "QUIN_TDM_TX_4"
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#define LPASS_BE_QUIN_TDM_RX_5 "QUIN_TDM_RX_5"
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#define LPASS_BE_QUIN_TDM_TX_5 "QUIN_TDM_TX_5"
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#define LPASS_BE_QUIN_TDM_RX_6 "QUIN_TDM_RX_6"
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#define LPASS_BE_QUIN_TDM_TX_6 "QUIN_TDM_TX_6"
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#define LPASS_BE_QUIN_TDM_RX_7 "QUIN_TDM_RX_7"
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#define LPASS_BE_QUIN_TDM_TX_7 "QUIN_TDM_TX_7"
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#define LPASS_BE_SEN_TDM_RX_0 "SEN_TDM_RX_0"
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#define LPASS_BE_SEN_TDM_TX_0 "SEN_TDM_TX_0"
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#define LPASS_BE_SEN_TDM_RX_1 "SEN_TDM_RX_1"
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#define LPASS_BE_SEN_TDM_TX_1 "SEN_TDM_TX_1"
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#define LPASS_BE_SEN_TDM_RX_2 "SEN_TDM_RX_2"
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#define LPASS_BE_SEN_TDM_TX_2 "SEN_TDM_TX_2"
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#define LPASS_BE_SEN_TDM_RX_3 "SEN_TDM_RX_3"
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#define LPASS_BE_SEN_TDM_TX_3 "SEN_TDM_TX_3"
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#define LPASS_BE_SEN_TDM_RX_4 "SEN_TDM_RX_4"
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#define LPASS_BE_SEN_TDM_TX_4 "SEN_TDM_TX_4"
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#define LPASS_BE_SEN_TDM_RX_5 "SEN_TDM_RX_5"
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#define LPASS_BE_SEN_TDM_TX_5 "SEN_TDM_TX_5"
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#define LPASS_BE_SEN_TDM_RX_6 "SEN_TDM_RX_6"
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#define LPASS_BE_SEN_TDM_TX_6 "SEN_TDM_TX_6"
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#define LPASS_BE_SEN_TDM_RX_7 "SEN_TDM_RX_7"
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#define LPASS_BE_SEN_TDM_TX_7 "SEN_TDM_TX_7"
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#define LPASS_BE_SLIMBUS_7_RX "SLIMBUS_7_RX"
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#define LPASS_BE_SLIMBUS_7_TX "SLIMBUS_7_TX"
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#define LPASS_BE_SLIMBUS_8_RX "SLIMBUS_8_RX"
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#define LPASS_BE_SLIMBUS_8_TX "SLIMBUS_8_TX"
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#define LPASS_BE_SLIMBUS_9_RX "SLIMBUS_9_RX"
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#define LPASS_BE_SLIMBUS_9_TX "SLIMBUS_9_TX"
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#define LPASS_BE_USB_AUDIO_RX "USB_AUDIO_RX"
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#define LPASS_BE_USB_AUDIO_TX "USB_AUDIO_TX"
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#define LPASS_BE_INT0_MI2S_RX "INT0_MI2S_RX"
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#define LPASS_BE_INT0_MI2S_TX "INT0_MI2S_TX"
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#define LPASS_BE_INT1_MI2S_RX "INT1_MI2S_RX"
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#define LPASS_BE_INT1_MI2S_TX "INT1_MI2S_TX"
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#define LPASS_BE_INT2_MI2S_RX "INT2_MI2S_RX"
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#define LPASS_BE_INT2_MI2S_TX "INT2_MI2S_TX"
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#define LPASS_BE_INT3_MI2S_RX "INT3_MI2S_RX"
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#define LPASS_BE_INT3_MI2S_TX "INT3_MI2S_TX"
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#define LPASS_BE_INT4_MI2S_RX "INT4_MI2S_RX"
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#define LPASS_BE_INT4_MI2S_TX "INT4_MI2S_TX"
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#define LPASS_BE_INT5_MI2S_RX "INT5_MI2S_RX"
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#define LPASS_BE_INT5_MI2S_TX "INT5_MI2S_TX"
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#define LPASS_BE_INT6_MI2S_RX "INT6_MI2S_RX"
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#define LPASS_BE_INT6_MI2S_TX "INT6_MI2S_TX"
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#define LPASS_BE_WSA_CDC_DMA_RX_0 "WSA_CDC_DMA_RX_0"
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#define LPASS_BE_WSA_CDC_DMA_TX_0 "WSA_CDC_DMA_TX_0"
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#define LPASS_BE_WSA_CDC_DMA_RX_1 "WSA_CDC_DMA_RX_1"
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#define LPASS_BE_WSA_CDC_DMA_TX_1 "WSA_CDC_DMA_TX_1"
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#define LPASS_BE_WSA_CDC_DMA_TX_2 "WSA_CDC_DMA_TX_2"
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#define LPASS_BE_VA_CDC_DMA_TX_0 "VA_CDC_DMA_TX_0"
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#define LPASS_BE_VA_CDC_DMA_TX_1 "VA_CDC_DMA_TX_1"
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#define LPASS_BE_VA_CDC_DMA_TX_2 "VA_CDC_DMA_TX_2"
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#define LPASS_BE_RX_CDC_DMA_RX_0 "RX_CDC_DMA_RX_0"
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#define LPASS_BE_RX_CDC_DMA_RX_1 "RX_CDC_DMA_RX_1"
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#define LPASS_BE_RX_CDC_DMA_RX_2 "RX_CDC_DMA_RX_2"
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#define LPASS_BE_RX_CDC_DMA_RX_3 "RX_CDC_DMA_RX_3"
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#define LPASS_BE_RX_CDC_DMA_RX_4 "RX_CDC_DMA_RX_4"
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#define LPASS_BE_RX_CDC_DMA_RX_5 "RX_CDC_DMA_RX_5"
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#define LPASS_BE_RX_CDC_DMA_RX_6 "RX_CDC_DMA_RX_6"
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#define LPASS_BE_RX_CDC_DMA_RX_7 "RX_CDC_DMA_RX_7"
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#define LPASS_BE_TX_CDC_DMA_TX_0 "TX_CDC_DMA_TX_0"
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#define LPASS_BE_TX_CDC_DMA_TX_1 "TX_CDC_DMA_TX_1"
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#define LPASS_BE_TX_CDC_DMA_TX_2 "TX_CDC_DMA_TX_2"
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#define LPASS_BE_TX_CDC_DMA_TX_3 "TX_CDC_DMA_TX_3"
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#define LPASS_BE_TX_CDC_DMA_TX_4 "TX_CDC_DMA_TX_4"
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#define LPASS_BE_TX_CDC_DMA_TX_5 "TX_CDC_DMA_TX_5"
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/* For multimedia front-ends, asm session is allocated dynamically.
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* Hence, asm session/multimedia front-end mapping has to be maintained.
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* Due to this reason, additional multimedia front-end must be placed before
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* non-multimedia front-ends.
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*/
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enum {
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MSM_FRONTEND_DAI_MULTIMEDIA1 = 0,
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MSM_FRONTEND_DAI_MULTIMEDIA2,
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MSM_FRONTEND_DAI_MULTIMEDIA3,
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MSM_FRONTEND_DAI_MULTIMEDIA4,
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MSM_FRONTEND_DAI_MULTIMEDIA5,
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MSM_FRONTEND_DAI_MULTIMEDIA6,
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MSM_FRONTEND_DAI_MULTIMEDIA7,
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MSM_FRONTEND_DAI_MULTIMEDIA8,
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MSM_FRONTEND_DAI_MULTIMEDIA9,
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MSM_FRONTEND_DAI_MULTIMEDIA10,
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MSM_FRONTEND_DAI_MULTIMEDIA11,
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MSM_FRONTEND_DAI_MULTIMEDIA12,
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MSM_FRONTEND_DAI_MULTIMEDIA13,
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MSM_FRONTEND_DAI_MULTIMEDIA14,
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MSM_FRONTEND_DAI_MULTIMEDIA15,
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MSM_FRONTEND_DAI_MULTIMEDIA16,
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MSM_FRONTEND_DAI_MULTIMEDIA17,
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MSM_FRONTEND_DAI_MULTIMEDIA18,
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MSM_FRONTEND_DAI_MULTIMEDIA19,
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MSM_FRONTEND_DAI_MULTIMEDIA20,
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MSM_FRONTEND_DAI_MULTIMEDIA21,
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MSM_FRONTEND_DAI_MULTIMEDIA22,
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MSM_FRONTEND_DAI_MULTIMEDIA23,
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MSM_FRONTEND_DAI_MULTIMEDIA24,
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MSM_FRONTEND_DAI_MULTIMEDIA25,
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MSM_FRONTEND_DAI_MULTIMEDIA26,
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MSM_FRONTEND_DAI_MULTIMEDIA27,
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MSM_FRONTEND_DAI_MULTIMEDIA28,
|
|
MSM_FRONTEND_DAI_MULTIMEDIA29,
|
|
MSM_FRONTEND_DAI_MULTIMEDIA30,
|
|
MSM_FRONTEND_DAI_VOIP,
|
|
MSM_FRONTEND_DAI_AFE_RX,
|
|
MSM_FRONTEND_DAI_AFE_TX,
|
|
MSM_FRONTEND_DAI_VOICE_STUB,
|
|
MSM_FRONTEND_DAI_DTMF_RX,
|
|
MSM_FRONTEND_DAI_QCHAT,
|
|
MSM_FRONTEND_DAI_VOLTE_STUB,
|
|
MSM_FRONTEND_DAI_LSM1,
|
|
MSM_FRONTEND_DAI_LSM2,
|
|
MSM_FRONTEND_DAI_LSM3,
|
|
MSM_FRONTEND_DAI_LSM4,
|
|
MSM_FRONTEND_DAI_LSM5,
|
|
MSM_FRONTEND_DAI_LSM6,
|
|
MSM_FRONTEND_DAI_LSM7,
|
|
MSM_FRONTEND_DAI_LSM8,
|
|
MSM_FRONTEND_DAI_VOICE2_STUB,
|
|
MSM_FRONTEND_DAI_VOICEMMODE1,
|
|
MSM_FRONTEND_DAI_VOICEMMODE2,
|
|
MSM_FRONTEND_DAI_MAX,
|
|
};
|
|
|
|
#define MSM_FRONTEND_DAI_MM_SIZE (MSM_FRONTEND_DAI_MULTIMEDIA30 + 1)
|
|
#define MSM_FRONTEND_DAI_MM_MAX_ID MSM_FRONTEND_DAI_MULTIMEDIA30
|
|
|
|
enum {
|
|
MSM_BACKEND_DAI_PRI_I2S_RX = 0,
|
|
MSM_BACKEND_DAI_PRI_I2S_TX,
|
|
MSM_BACKEND_DAI_SLIMBUS_0_RX,
|
|
MSM_BACKEND_DAI_SLIMBUS_0_TX,
|
|
MSM_BACKEND_DAI_HDMI_RX,
|
|
MSM_BACKEND_DAI_INT_BT_SCO_RX,
|
|
MSM_BACKEND_DAI_INT_BT_SCO_TX,
|
|
MSM_BACKEND_DAI_INT_FM_RX,
|
|
MSM_BACKEND_DAI_INT_FM_TX,
|
|
MSM_BACKEND_DAI_AFE_PCM_RX,
|
|
MSM_BACKEND_DAI_AFE_PCM_TX,
|
|
MSM_BACKEND_DAI_AUXPCM_RX,
|
|
MSM_BACKEND_DAI_AUXPCM_TX,
|
|
MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
|
|
MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
|
|
MSM_BACKEND_DAI_INCALL_RECORD_RX,
|
|
MSM_BACKEND_DAI_INCALL_RECORD_TX,
|
|
MSM_BACKEND_DAI_MI2S_RX,
|
|
MSM_BACKEND_DAI_MI2S_TX,
|
|
MSM_BACKEND_DAI_SEC_I2S_RX,
|
|
MSM_BACKEND_DAI_SLIMBUS_1_RX,
|
|
MSM_BACKEND_DAI_SLIMBUS_1_TX,
|
|
MSM_BACKEND_DAI_SLIMBUS_2_RX,
|
|
MSM_BACKEND_DAI_SLIMBUS_2_TX,
|
|
MSM_BACKEND_DAI_SLIMBUS_3_RX,
|
|
MSM_BACKEND_DAI_SLIMBUS_3_TX,
|
|
MSM_BACKEND_DAI_SLIMBUS_4_RX,
|
|
MSM_BACKEND_DAI_SLIMBUS_4_TX,
|
|
MSM_BACKEND_DAI_SLIMBUS_5_RX,
|
|
MSM_BACKEND_DAI_SLIMBUS_5_TX,
|
|
MSM_BACKEND_DAI_SLIMBUS_6_RX,
|
|
MSM_BACKEND_DAI_SLIMBUS_6_TX,
|
|
MSM_BACKEND_DAI_SLIMBUS_7_RX,
|
|
MSM_BACKEND_DAI_SLIMBUS_7_TX,
|
|
MSM_BACKEND_DAI_SLIMBUS_8_RX,
|
|
MSM_BACKEND_DAI_SLIMBUS_8_TX,
|
|
MSM_BACKEND_DAI_EXTPROC_RX,
|
|
MSM_BACKEND_DAI_EXTPROC_TX,
|
|
MSM_BACKEND_DAI_EXTPROC_EC_TX,
|
|
MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
|
|
MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
|
|
MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
|
|
MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
|
|
MSM_BACKEND_DAI_PRI_MI2S_RX,
|
|
MSM_BACKEND_DAI_PRI_MI2S_TX,
|
|
MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
|
|
MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
|
|
MSM_BACKEND_DAI_AUDIO_I2S_RX,
|
|
MSM_BACKEND_DAI_SEC_AUXPCM_RX,
|
|
MSM_BACKEND_DAI_SEC_AUXPCM_TX,
|
|
MSM_BACKEND_DAI_PRI_SPDIF_RX,
|
|
MSM_BACKEND_DAI_SECONDARY_MI2S_RX_SD1,
|
|
MSM_BACKEND_DAI_QUINARY_MI2S_RX,
|
|
MSM_BACKEND_DAI_QUINARY_MI2S_TX,
|
|
MSM_BACKEND_DAI_SENARY_MI2S_TX,
|
|
MSM_BACKEND_DAI_PRI_TDM_RX_0,
|
|
MSM_BACKEND_DAI_PRI_TDM_TX_0,
|
|
MSM_BACKEND_DAI_PRI_TDM_RX_1,
|
|
MSM_BACKEND_DAI_PRI_TDM_TX_1,
|
|
MSM_BACKEND_DAI_PRI_TDM_RX_2,
|
|
MSM_BACKEND_DAI_PRI_TDM_TX_2,
|
|
MSM_BACKEND_DAI_PRI_TDM_RX_3,
|
|
MSM_BACKEND_DAI_PRI_TDM_TX_3,
|
|
MSM_BACKEND_DAI_PRI_TDM_RX_4,
|
|
MSM_BACKEND_DAI_PRI_TDM_TX_4,
|
|
MSM_BACKEND_DAI_PRI_TDM_RX_5,
|
|
MSM_BACKEND_DAI_PRI_TDM_TX_5,
|
|
MSM_BACKEND_DAI_PRI_TDM_RX_6,
|
|
MSM_BACKEND_DAI_PRI_TDM_TX_6,
|
|
MSM_BACKEND_DAI_PRI_TDM_RX_7,
|
|
MSM_BACKEND_DAI_PRI_TDM_TX_7,
|
|
MSM_BACKEND_DAI_SEC_TDM_RX_0,
|
|
MSM_BACKEND_DAI_SEC_TDM_TX_0,
|
|
MSM_BACKEND_DAI_SEC_TDM_RX_1,
|
|
MSM_BACKEND_DAI_SEC_TDM_TX_1,
|
|
MSM_BACKEND_DAI_SEC_TDM_RX_2,
|
|
MSM_BACKEND_DAI_SEC_TDM_TX_2,
|
|
MSM_BACKEND_DAI_SEC_TDM_RX_3,
|
|
MSM_BACKEND_DAI_SEC_TDM_TX_3,
|
|
MSM_BACKEND_DAI_SEC_TDM_RX_4,
|
|
MSM_BACKEND_DAI_SEC_TDM_TX_4,
|
|
MSM_BACKEND_DAI_SEC_TDM_RX_5,
|
|
MSM_BACKEND_DAI_SEC_TDM_TX_5,
|
|
MSM_BACKEND_DAI_SEC_TDM_RX_6,
|
|
MSM_BACKEND_DAI_SEC_TDM_TX_6,
|
|
MSM_BACKEND_DAI_SEC_TDM_RX_7,
|
|
MSM_BACKEND_DAI_SEC_TDM_TX_7,
|
|
MSM_BACKEND_DAI_TERT_TDM_RX_0,
|
|
MSM_BACKEND_DAI_TERT_TDM_TX_0,
|
|
MSM_BACKEND_DAI_TERT_TDM_RX_1,
|
|
MSM_BACKEND_DAI_TERT_TDM_TX_1,
|
|
MSM_BACKEND_DAI_TERT_TDM_RX_2,
|
|
MSM_BACKEND_DAI_TERT_TDM_TX_2,
|
|
MSM_BACKEND_DAI_TERT_TDM_RX_3,
|
|
MSM_BACKEND_DAI_TERT_TDM_TX_3,
|
|
MSM_BACKEND_DAI_TERT_TDM_RX_4,
|
|
MSM_BACKEND_DAI_TERT_TDM_TX_4,
|
|
MSM_BACKEND_DAI_TERT_TDM_RX_5,
|
|
MSM_BACKEND_DAI_TERT_TDM_TX_5,
|
|
MSM_BACKEND_DAI_TERT_TDM_RX_6,
|
|
MSM_BACKEND_DAI_TERT_TDM_TX_6,
|
|
MSM_BACKEND_DAI_TERT_TDM_RX_7,
|
|
MSM_BACKEND_DAI_TERT_TDM_TX_7,
|
|
MSM_BACKEND_DAI_QUAT_TDM_RX_0,
|
|
MSM_BACKEND_DAI_QUAT_TDM_TX_0,
|
|
MSM_BACKEND_DAI_QUAT_TDM_RX_1,
|
|
MSM_BACKEND_DAI_QUAT_TDM_TX_1,
|
|
MSM_BACKEND_DAI_QUAT_TDM_RX_2,
|
|
MSM_BACKEND_DAI_QUAT_TDM_TX_2,
|
|
MSM_BACKEND_DAI_QUAT_TDM_RX_3,
|
|
MSM_BACKEND_DAI_QUAT_TDM_TX_3,
|
|
MSM_BACKEND_DAI_QUAT_TDM_RX_4,
|
|
MSM_BACKEND_DAI_QUAT_TDM_TX_4,
|
|
MSM_BACKEND_DAI_QUAT_TDM_RX_5,
|
|
MSM_BACKEND_DAI_QUAT_TDM_TX_5,
|
|
MSM_BACKEND_DAI_QUAT_TDM_RX_6,
|
|
MSM_BACKEND_DAI_QUAT_TDM_TX_6,
|
|
MSM_BACKEND_DAI_QUAT_TDM_RX_7,
|
|
MSM_BACKEND_DAI_QUAT_TDM_TX_7,
|
|
MSM_BACKEND_DAI_QUIN_TDM_RX_0,
|
|
MSM_BACKEND_DAI_QUIN_TDM_TX_0,
|
|
MSM_BACKEND_DAI_QUIN_TDM_RX_1,
|
|
MSM_BACKEND_DAI_QUIN_TDM_TX_1,
|
|
MSM_BACKEND_DAI_QUIN_TDM_RX_2,
|
|
MSM_BACKEND_DAI_QUIN_TDM_TX_2,
|
|
MSM_BACKEND_DAI_QUIN_TDM_RX_3,
|
|
MSM_BACKEND_DAI_QUIN_TDM_TX_3,
|
|
MSM_BACKEND_DAI_QUIN_TDM_RX_4,
|
|
MSM_BACKEND_DAI_QUIN_TDM_TX_4,
|
|
MSM_BACKEND_DAI_QUIN_TDM_RX_5,
|
|
MSM_BACKEND_DAI_QUIN_TDM_TX_5,
|
|
MSM_BACKEND_DAI_QUIN_TDM_RX_6,
|
|
MSM_BACKEND_DAI_QUIN_TDM_TX_6,
|
|
MSM_BACKEND_DAI_QUIN_TDM_RX_7,
|
|
MSM_BACKEND_DAI_QUIN_TDM_TX_7,
|
|
MSM_BACKEND_DAI_SEN_TDM_RX_0,
|
|
MSM_BACKEND_DAI_SEN_TDM_TX_0,
|
|
MSM_BACKEND_DAI_SEN_TDM_RX_1,
|
|
MSM_BACKEND_DAI_SEN_TDM_TX_1,
|
|
MSM_BACKEND_DAI_SEN_TDM_RX_2,
|
|
MSM_BACKEND_DAI_SEN_TDM_TX_2,
|
|
MSM_BACKEND_DAI_SEN_TDM_RX_3,
|
|
MSM_BACKEND_DAI_SEN_TDM_TX_3,
|
|
MSM_BACKEND_DAI_SEN_TDM_RX_4,
|
|
MSM_BACKEND_DAI_SEN_TDM_TX_4,
|
|
MSM_BACKEND_DAI_SEN_TDM_RX_5,
|
|
MSM_BACKEND_DAI_SEN_TDM_TX_5,
|
|
MSM_BACKEND_DAI_SEN_TDM_RX_6,
|
|
MSM_BACKEND_DAI_SEN_TDM_TX_6,
|
|
MSM_BACKEND_DAI_SEN_TDM_RX_7,
|
|
MSM_BACKEND_DAI_SEN_TDM_TX_7,
|
|
MSM_BACKEND_DAI_INT_BT_A2DP_RX,
|
|
MSM_BACKEND_DAI_USB_RX,
|
|
MSM_BACKEND_DAI_USB_TX,
|
|
MSM_BACKEND_DAI_DISPLAY_PORT_RX,
|
|
MSM_BACKEND_DAI_DISPLAY_PORT_RX_1,
|
|
MSM_BACKEND_DAI_TERT_AUXPCM_RX,
|
|
MSM_BACKEND_DAI_TERT_AUXPCM_TX,
|
|
MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
|
|
MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
|
|
MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
|
|
MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
|
|
MSM_BACKEND_DAI_INT0_MI2S_RX,
|
|
MSM_BACKEND_DAI_INT0_MI2S_TX,
|
|
MSM_BACKEND_DAI_INT1_MI2S_RX,
|
|
MSM_BACKEND_DAI_INT1_MI2S_TX,
|
|
MSM_BACKEND_DAI_INT2_MI2S_RX,
|
|
MSM_BACKEND_DAI_INT2_MI2S_TX,
|
|
MSM_BACKEND_DAI_INT3_MI2S_RX,
|
|
MSM_BACKEND_DAI_INT3_MI2S_TX,
|
|
MSM_BACKEND_DAI_INT4_MI2S_RX,
|
|
MSM_BACKEND_DAI_INT4_MI2S_TX,
|
|
MSM_BACKEND_DAI_INT5_MI2S_RX,
|
|
MSM_BACKEND_DAI_INT5_MI2S_TX,
|
|
MSM_BACKEND_DAI_INT6_MI2S_RX,
|
|
MSM_BACKEND_DAI_INT6_MI2S_TX,
|
|
MSM_BACKEND_DAI_SEN_AUXPCM_RX,
|
|
MSM_BACKEND_DAI_SEN_AUXPCM_TX,
|
|
MSM_BACKEND_DAI_SENARY_MI2S_RX,
|
|
MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
|
|
MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
|
|
MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
|
|
MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
|
|
MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2,
|
|
MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
|
|
MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
|
|
MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
|
|
MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
|
|
MSM_BACKEND_DAI_TX_CDC_DMA_TX_0,
|
|
MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
|
|
MSM_BACKEND_DAI_TX_CDC_DMA_TX_1,
|
|
MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
|
|
MSM_BACKEND_DAI_TX_CDC_DMA_TX_2,
|
|
MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
|
|
MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
|
|
MSM_BACKEND_DAI_RX_CDC_DMA_RX_4,
|
|
MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
|
|
MSM_BACKEND_DAI_RX_CDC_DMA_RX_5,
|
|
MSM_BACKEND_DAI_TX_CDC_DMA_TX_5,
|
|
MSM_BACKEND_DAI_RX_CDC_DMA_RX_6,
|
|
MSM_BACKEND_DAI_RX_CDC_DMA_RX_7,
|
|
MSM_BACKEND_DAI_PRI_SPDIF_TX,
|
|
MSM_BACKEND_DAI_SEC_SPDIF_RX,
|
|
MSM_BACKEND_DAI_SEC_SPDIF_TX,
|
|
MSM_BACKEND_DAI_SLIMBUS_9_RX,
|
|
MSM_BACKEND_DAI_SLIMBUS_9_TX,
|
|
MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
|
|
MSM_BACKEND_DAI_PRI_META_MI2S_RX,
|
|
MSM_BACKEND_DAI_SEC_META_MI2S_RX,
|
|
MSM_BACKEND_DAI_PROXY_RX,
|
|
MSM_BACKEND_DAI_PROXY_TX,
|
|
MSM_BACKEND_DAI_HDMI_RX_MS,
|
|
MSM_BACKEND_DAI_MAX,
|
|
};
|
|
|
|
enum msm_pcm_routing_event {
|
|
MSM_PCM_RT_EVT_BUF_RECFG,
|
|
MSM_PCM_RT_EVT_DEVSWITCH,
|
|
MSM_PCM_RT_EVT_MAX,
|
|
};
|
|
|
|
enum {
|
|
EXT_EC_REF_NONE = 0,
|
|
EXT_EC_REF_PRI_MI2S_TX,
|
|
EXT_EC_REF_SEC_MI2S_TX,
|
|
EXT_EC_REF_TERT_MI2S_TX,
|
|
EXT_EC_REF_QUAT_MI2S_TX,
|
|
EXT_EC_REF_QUIN_MI2S_TX,
|
|
EXT_EC_REF_SLIM_1_TX,
|
|
EXT_EC_REF_PRI_TDM_TX,
|
|
EXT_EC_REF_SEC_TDM_TX,
|
|
};
|
|
|
|
#define INVALID_SESSION -1
|
|
#define SESSION_TYPE_RX 0
|
|
#define SESSION_TYPE_TX 1
|
|
#define MAX_SESSION_TYPES 2
|
|
#define INT_RX_VOL_MAX_STEPS 0x2000
|
|
#define INT_RX_VOL_GAIN 0x2000
|
|
|
|
#define RELEASE_LOCK 0
|
|
#define ACQUIRE_LOCK 1
|
|
|
|
#define MSM_BACKEND_DAI_PP_PARAMS_REQ_MAX 3
|
|
#define HDMI_RX_ID 0x8001
|
|
#define ADM_PP_PARAM_MUTE_ID 0
|
|
#define ADM_PP_PARAM_MUTE_BIT 1
|
|
#define ADM_PP_PARAM_LATENCY_ID 1
|
|
#define ADM_PP_PARAM_LATENCY_BIT 2
|
|
#define BE_DAI_PORT_SESSIONS_IDX_MAX 4
|
|
#define BE_DAI_FE_SESSIONS_IDX_MAX 2
|
|
|
|
#define STREAM_TYPE_ASM 0
|
|
#define STREAM_TYPE_LSM 1
|
|
|
|
enum {
|
|
ADM_TOPOLOGY_CAL_TYPE_IDX = 0,
|
|
ADM_LSM_TOPOLOGY_CAL_TYPE_IDX,
|
|
MAX_ROUTING_CAL_TYPES
|
|
};
|
|
|
|
struct msm_pcm_routing_evt {
|
|
void (*event_func)(enum msm_pcm_routing_event, void *);
|
|
void *priv_data;
|
|
};
|
|
|
|
struct msm_pcm_routing_bdai_data {
|
|
u16 port_id; /* AFE port ID */
|
|
u8 active; /* track if this backend is enabled */
|
|
|
|
/* Front-end sessions */
|
|
unsigned long fe_sessions[BE_DAI_FE_SESSIONS_IDX_MAX];
|
|
/*
|
|
* Track Tx BE ports -> Rx BE ports.
|
|
* port_sessions[0] used to track BE 0 to BE 63.
|
|
* port_sessions[1] used to track BE 64 to BE 127.
|
|
* port_sessions[2] used to track BE 128 to BE 191.
|
|
* port_sessions[3] used to track BE 192 to BE 255.
|
|
*/
|
|
u64 port_sessions[BE_DAI_PORT_SESSIONS_IDX_MAX];
|
|
|
|
unsigned int sample_rate;
|
|
unsigned int channel;
|
|
unsigned int format;
|
|
unsigned int adm_override_ch;
|
|
char *name;
|
|
};
|
|
|
|
struct msm_pcm_routing_fdai_data {
|
|
u16 be_srate; /* track prior backend sample rate for flushing purpose */
|
|
int strm_id; /* ASM stream ID */
|
|
int perf_mode;
|
|
struct msm_pcm_routing_evt event_info;
|
|
u32 passthr_mode;
|
|
};
|
|
|
|
#define MAX_APP_TYPES 16
|
|
struct msm_pcm_routing_app_type_data {
|
|
int app_type;
|
|
u32 sample_rate;
|
|
int bit_width;
|
|
u32 num_out_channels;
|
|
};
|
|
|
|
struct msm_pcm_stream_app_type_cfg {
|
|
int app_type;
|
|
int acdb_dev_id;
|
|
int sample_rate;
|
|
};
|
|
|
|
/* dai_id: front-end ID,
|
|
* dspst_id: DSP audio stream ID
|
|
* stream_type: playback or capture
|
|
*/
|
|
int msm_pcm_routing_reg_phy_stream(int fedai_id, int perf_mode, int dspst_id,
|
|
int stream_type);
|
|
void msm_pcm_routing_reg_psthr_stream(int fedai_id, int dspst_id,
|
|
int stream_type);
|
|
int msm_pcm_routing_reg_phy_compr_stream(int fedai_id, int perf_mode,
|
|
int dspst_id, int stream_type,
|
|
uint32_t compr_passthr);
|
|
|
|
int msm_pcm_routing_reg_phy_stream_v2(int fedai_id, int perf_mode,
|
|
int dspst_id, int stream_type,
|
|
struct msm_pcm_routing_evt event_info);
|
|
|
|
void msm_pcm_routing_dereg_phy_stream(int fedai_id, int stream_type);
|
|
|
|
int msm_routing_check_backend_enabled(int fedai_id);
|
|
|
|
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void msm_pcm_routing_get_bedai_info(int be_idx,
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struct msm_pcm_routing_bdai_data *bedai);
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void msm_pcm_routing_get_fedai_info(int fe_idx, int sess_type,
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struct msm_pcm_routing_fdai_data *fe_dai);
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void msm_pcm_routing_acquire_lock(void);
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void msm_pcm_routing_release_lock(void);
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int msm_pcm_routing_reg_stream_app_type_cfg(
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int fedai_id, int session_type, int be_id,
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struct msm_pcm_stream_app_type_cfg *cfg_data);
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int msm_pcm_routing_get_stream_app_type_cfg(
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int fedai_id, int session_type, int *be_id,
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struct msm_pcm_stream_app_type_cfg *cfg_data);
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int msm_pcm_routing_send_chmix_cfg(int fe_id, int ip_channel_cnt,
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int op_channel_cnt, int *ch_wght_coeff,
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int session_type, int stream_type);
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int msm_pcm_routing_get_pp_ch_cnt(int fe_id, int session_type);
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int msm_pcm_routing_set_channel_mixer_cfg(
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int fe_id, int session_type,
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struct msm_pcm_channel_mixer *params);
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int msm_pcm_routing_set_channel_mixer_runtime(
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int be_id, int session_id,
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int session_type,
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struct msm_pcm_channel_mixer *params);
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#endif /*_MSM_PCM_H*/
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