0b39db28b9
Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
233 lines
3.9 KiB
ArmAsm
233 lines
3.9 KiB
ArmAsm
/*
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* BF561 coreB bootstrap file
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*
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* Copyright 2007-2009 Analog Devices Inc.
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* Philippe Gerum <rpm@xenomai.org>
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/blackfin.h>
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#include <asm/asm-offsets.h>
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#include <asm/trace.h>
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__INIT
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/* Lay the initial stack into the L1 scratch area of Core B */
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#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
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ENTRY(_coreb_trampoline_start)
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/* Set the SYSCFG register */
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R0 = 0x36;
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SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
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R0 = 0;
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/*Clear Out All the data and pointer Registers*/
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R1 = R0;
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R2 = R0;
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R3 = R0;
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R4 = R0;
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R5 = R0;
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R6 = R0;
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R7 = R0;
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P0 = R0;
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P1 = R0;
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P2 = R0;
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P3 = R0;
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P4 = R0;
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P5 = R0;
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LC0 = r0;
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LC1 = r0;
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L0 = r0;
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L1 = r0;
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L2 = r0;
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L3 = r0;
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/* Clear Out All the DAG Registers*/
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B0 = r0;
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B1 = r0;
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B2 = r0;
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B3 = r0;
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I0 = r0;
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I1 = r0;
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I2 = r0;
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I3 = r0;
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M0 = r0;
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M1 = r0;
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M2 = r0;
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M3 = r0;
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trace_buffer_init(p0,r0);
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/* Turn off the icache */
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p0.l = LO(IMEM_CONTROL);
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p0.h = HI(IMEM_CONTROL);
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R1 = [p0];
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R0 = ~ENICPLB;
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R0 = R0 & R1;
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/* Disabling of CPLBs should be proceeded by a CSYNC */
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CSYNC;
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[p0] = R0;
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SSYNC;
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/* Turn off the dcache */
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p0.l = LO(DMEM_CONTROL);
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p0.h = HI(DMEM_CONTROL);
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R1 = [p0];
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R0 = ~ENDCPLB;
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R0 = R0 & R1;
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/* Disabling of CPLBs should be proceeded by a CSYNC */
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CSYNC;
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[p0] = R0;
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SSYNC;
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/* in case of double faults, save a few things */
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p0.l = _init_retx_coreb;
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p0.h = _init_retx_coreb;
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R0 = RETX;
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[P0] = R0;
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#ifdef CONFIG_DEBUG_DOUBLEFAULT
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/* Only save these if we are storing them,
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* This happens here, since L1 gets clobbered
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* below
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*/
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GET_PDA(p0, r0);
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r7 = [p0 + PDA_DF_RETX];
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p1.l = _init_saved_retx_coreb;
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p1.h = _init_saved_retx_coreb;
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[p1] = r7;
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r7 = [p0 + PDA_DF_DCPLB];
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p1.l = _init_saved_dcplb_fault_addr_coreb;
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p1.h = _init_saved_dcplb_fault_addr_coreb;
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[p1] = r7;
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r7 = [p0 + PDA_DF_ICPLB];
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p1.l = _init_saved_icplb_fault_addr_coreb;
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p1.h = _init_saved_icplb_fault_addr_coreb;
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[p1] = r7;
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r7 = [p0 + PDA_DF_SEQSTAT];
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p1.l = _init_saved_seqstat_coreb;
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p1.h = _init_saved_seqstat_coreb;
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[p1] = r7;
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#endif
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/* Initialize stack pointer */
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sp.l = lo(INITIAL_STACK);
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sp.h = hi(INITIAL_STACK);
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fp = sp;
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usp = sp;
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/* This section keeps the processor in supervisor mode
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* during core B startup. Branches to the idle task.
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*/
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/* EVT15 = _real_start */
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p0.l = lo(EVT15);
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p0.h = hi(EVT15);
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p1.l = _coreb_start;
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p1.h = _coreb_start;
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[p0] = p1;
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csync;
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p0.l = lo(IMASK);
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p0.h = hi(IMASK);
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p1.l = IMASK_IVG15;
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p1.h = 0x0;
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[p0] = p1;
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csync;
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raise 15;
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p0.l = .LWAIT_HERE;
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p0.h = .LWAIT_HERE;
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reti = p0;
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#if defined(ANOMALY_05000281)
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nop; nop; nop;
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#endif
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rti;
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.LWAIT_HERE:
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jump .LWAIT_HERE;
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ENDPROC(_coreb_trampoline_start)
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ENTRY(_coreb_trampoline_end)
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.section ".text"
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ENTRY(_set_sicb_iwr)
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P0.H = hi(SICB_IWR0);
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P0.L = lo(SICB_IWR0);
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P1.H = hi(SICB_IWR1);
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P1.L = lo(SICB_IWR1);
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[P0] = R0;
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[P1] = R1;
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SSYNC;
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RTS;
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ENDPROC(_set_sicb_iwr)
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ENTRY(_coreb_sleep)
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sp.l = lo(INITIAL_STACK);
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sp.h = hi(INITIAL_STACK);
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fp = sp;
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usp = sp;
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call _set_sicb_iwr;
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CLI R2;
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SSYNC;
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IDLE;
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STI R2;
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R0 = IWR_DISABLE_ALL;
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R1 = IWR_DISABLE_ALL;
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call _set_sicb_iwr;
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p0.h = hi(COREB_L1_CODE_START);
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p0.l = lo(COREB_L1_CODE_START);
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jump (p0);
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ENDPROC(_coreb_sleep)
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__CPUINIT
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ENTRY(_coreb_start)
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[--sp] = reti;
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p0.l = lo(WDOGB_CTL);
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p0.h = hi(WDOGB_CTL);
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r0 = 0xAD6(z);
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w[p0] = r0; /* Clear the watchdog. */
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ssync;
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/*
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* switch to IDLE stack.
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*/
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p0.l = _secondary_stack;
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p0.h = _secondary_stack;
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sp = [p0];
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usp = sp;
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fp = sp;
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#ifdef CONFIG_HOTPLUG_CPU
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p0.l = _hotplug_coreb;
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p0.h = _hotplug_coreb;
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r0 = [p0];
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cc = BITTST(r0, 0);
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if cc jump 3f;
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#endif
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sp += -12;
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call _init_pda
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sp += 12;
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#ifdef CONFIG_HOTPLUG_CPU
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3:
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#endif
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call _secondary_start_kernel;
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.L_exit:
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jump.s .L_exit;
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ENDPROC(_coreb_start)
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