9f5336915b
Use BIT() macro whenever it is sensible to do so. Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Alexander Shishkin <virtuoso@slind.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
157 lines
4.7 KiB
C
157 lines
4.7 KiB
C
/*
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* linux/arch/arm/include/asm/hardware/coresight.h
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*
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* CoreSight components' registers
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*
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* Copyright (C) 2009 Nokia Corporation.
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* Alexander Shishkin
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_HARDWARE_CORESIGHT_H
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#define __ASM_HARDWARE_CORESIGHT_H
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#define TRACER_ACCESSED_BIT 0
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#define TRACER_RUNNING_BIT 1
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#define TRACER_CYCLE_ACC_BIT 2
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#define TRACER_ACCESSED BIT(TRACER_ACCESSED_BIT)
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#define TRACER_RUNNING BIT(TRACER_RUNNING_BIT)
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#define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT)
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#define TRACER_TIMEOUT 10000
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#define etm_writel(t, v, x) \
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(__raw_writel((v), (t)->etm_regs + (x)))
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#define etm_readl(t, x) (__raw_readl((t)->etm_regs + (x)))
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/* CoreSight Management Registers */
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#define CSMR_LOCKACCESS 0xfb0
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#define CSMR_LOCKSTATUS 0xfb4
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#define CSMR_AUTHSTATUS 0xfb8
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#define CSMR_DEVID 0xfc8
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#define CSMR_DEVTYPE 0xfcc
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/* CoreSight Component Registers */
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#define CSCR_CLASS 0xff4
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#define UNLOCK_MAGIC 0xc5acce55
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/* ETM control register, "ETM Architecture", 3.3.1 */
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#define ETMR_CTRL 0
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#define ETMCTRL_POWERDOWN 1
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#define ETMCTRL_PROGRAM (1 << 10)
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#define ETMCTRL_PORTSEL (1 << 11)
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#define ETMCTRL_DO_CONTEXTID (3 << 14)
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#define ETMCTRL_PORTMASK1 (7 << 4)
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#define ETMCTRL_PORTMASK2 (1 << 21)
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#define ETMCTRL_PORTMASK (ETMCTRL_PORTMASK1 | ETMCTRL_PORTMASK2)
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#define ETMCTRL_PORTSIZE(x) ((((x) & 7) << 4) | (!!((x) & 8)) << 21)
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#define ETMCTRL_DO_CPRT (1 << 1)
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#define ETMCTRL_DATAMASK (3 << 2)
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#define ETMCTRL_DATA_DO_DATA (1 << 2)
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#define ETMCTRL_DATA_DO_ADDR (1 << 3)
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#define ETMCTRL_DATA_DO_BOTH (ETMCTRL_DATA_DO_DATA | ETMCTRL_DATA_DO_ADDR)
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#define ETMCTRL_BRANCH_OUTPUT (1 << 8)
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#define ETMCTRL_CYCLEACCURATE (1 << 12)
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/* ETM configuration code register */
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#define ETMR_CONFCODE (0x04)
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/* ETM trace start/stop resource control register */
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#define ETMR_TRACESSCTRL (0x18)
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/* ETM trigger event register */
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#define ETMR_TRIGEVT (0x08)
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/* address access type register bits, "ETM architecture",
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* table 3-27 */
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/* - access type */
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#define ETMAAT_IFETCH 0
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#define ETMAAT_IEXEC 1
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#define ETMAAT_IEXECPASS 2
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#define ETMAAT_IEXECFAIL 3
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#define ETMAAT_DLOADSTORE 4
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#define ETMAAT_DLOAD 5
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#define ETMAAT_DSTORE 6
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/* - comparison access size */
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#define ETMAAT_JAVA (0 << 3)
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#define ETMAAT_THUMB (1 << 3)
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#define ETMAAT_ARM (3 << 3)
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/* - data value comparison control */
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#define ETMAAT_NOVALCMP (0 << 5)
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#define ETMAAT_VALMATCH (1 << 5)
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#define ETMAAT_VALNOMATCH (3 << 5)
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/* - exact match */
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#define ETMAAT_EXACTMATCH (1 << 7)
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/* - context id comparator control */
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#define ETMAAT_IGNCONTEXTID (0 << 8)
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#define ETMAAT_VALUE1 (1 << 8)
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#define ETMAAT_VALUE2 (2 << 8)
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#define ETMAAT_VALUE3 (3 << 8)
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/* - security level control */
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#define ETMAAT_IGNSECURITY (0 << 10)
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#define ETMAAT_NSONLY (1 << 10)
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#define ETMAAT_SONLY (2 << 10)
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#define ETMR_COMP_VAL(x) (0x40 + (x) * 4)
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#define ETMR_COMP_ACC_TYPE(x) (0x80 + (x) * 4)
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/* ETM status register, "ETM Architecture", 3.3.2 */
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#define ETMR_STATUS (0x10)
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#define ETMST_OVERFLOW BIT(0)
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#define ETMST_PROGBIT BIT(1)
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#define ETMST_STARTSTOP BIT(2)
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#define ETMST_TRIGGER BIT(3)
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#define etm_progbit(t) (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT)
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#define etm_started(t) (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP)
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#define etm_triggered(t) (etm_readl((t), ETMR_STATUS) & ETMST_TRIGGER)
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#define ETMR_TRACEENCTRL2 0x1c
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#define ETMR_TRACEENCTRL 0x24
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#define ETMTE_INCLEXCL BIT(24)
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#define ETMR_TRACEENEVT 0x20
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#define ETMCTRL_OPTS (ETMCTRL_DO_CPRT | \
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ETMCTRL_DATA_DO_ADDR | \
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ETMCTRL_BRANCH_OUTPUT | \
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ETMCTRL_DO_CONTEXTID)
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/* ETM management registers, "ETM Architecture", 3.5.24 */
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#define ETMMR_OSLAR 0x300
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#define ETMMR_OSLSR 0x304
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#define ETMMR_OSSRR 0x308
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#define ETMMR_PDSR 0x314
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/* ETB registers, "CoreSight Components TRM", 9.3 */
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#define ETBR_DEPTH 0x04
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#define ETBR_STATUS 0x0c
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#define ETBR_READMEM 0x10
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#define ETBR_READADDR 0x14
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#define ETBR_WRITEADDR 0x18
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#define ETBR_TRIGGERCOUNT 0x1c
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#define ETBR_CTRL 0x20
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#define ETBR_FORMATTERCTRL 0x304
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#define ETBFF_ENFTC 1
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#define ETBFF_ENFCONT BIT(1)
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#define ETBFF_FONFLIN BIT(4)
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#define ETBFF_MANUAL_FLUSH BIT(6)
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#define ETBFF_TRIGIN BIT(8)
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#define ETBFF_TRIGEVT BIT(9)
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#define ETBFF_TRIGFL BIT(10)
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#define etb_writel(t, v, x) \
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(__raw_writel((v), (t)->etb_regs + (x)))
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#define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x)))
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#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)
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#define etm_unlock(t) \
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do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
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#define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)
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#define etb_unlock(t) \
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do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
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#endif /* __ASM_HARDWARE_CORESIGHT_H */
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