475 lines
13 KiB
C
475 lines
13 KiB
C
/*
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* arch/arm/include/asm/cacheflush.h
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*
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* Copyright (C) 1999-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASMARM_CACHEFLUSH_H
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#define _ASMARM_CACHEFLUSH_H
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#include <linux/mm.h>
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#include <asm/glue.h>
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#include <asm/shmparam.h>
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#include <asm/cachetype.h>
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#include <asm/outercache.h>
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#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
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/*
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* Cache Model
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* ===========
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*/
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#undef _CACHE
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#undef MULTI_CACHE
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#if defined(CONFIG_CPU_CACHE_V3)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v3
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# endif
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#endif
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#if defined(CONFIG_CPU_CACHE_V4)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v4
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
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defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \
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defined(CONFIG_CPU_ARM1026)
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# define MULTI_CACHE 1
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#endif
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#if defined(CONFIG_CPU_FA526)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE fa
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM926T)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE arm926
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM940T)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE arm940
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM946E)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE arm946
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# endif
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#endif
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#if defined(CONFIG_CPU_CACHE_V4WB)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v4wb
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# endif
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#endif
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#if defined(CONFIG_CPU_XSCALE)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE xscale
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# endif
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#endif
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#if defined(CONFIG_CPU_XSC3)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE xsc3
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# endif
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#endif
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#if defined(CONFIG_CPU_MOHAWK)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE mohawk
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# endif
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#endif
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#if defined(CONFIG_CPU_FEROCEON)
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# define MULTI_CACHE 1
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#endif
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#if defined(CONFIG_CPU_V6)
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//# ifdef _CACHE
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# define MULTI_CACHE 1
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//# else
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//# define _CACHE v6
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//# endif
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#endif
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#if defined(CONFIG_CPU_V7)
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//# ifdef _CACHE
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# define MULTI_CACHE 1
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//# else
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//# define _CACHE v7
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//# endif
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#endif
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#if !defined(_CACHE) && !defined(MULTI_CACHE)
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#error Unknown cache maintainence model
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#endif
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/*
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* This flag is used to indicate that the page pointed to by a pte is clean
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* and does not require cleaning before returning it to the user.
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*/
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#define PG_dcache_clean PG_arch_1
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/*
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* MM Cache Management
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* ===================
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*
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* The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
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* implement these methods.
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*
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* Start addresses are inclusive and end addresses are exclusive;
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* start addresses should be rounded down, end addresses up.
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*
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* See Documentation/cachetlb.txt for more information.
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* Please note that the implementation of these, and the required
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* effects are cache-type (VIVT/VIPT/PIPT) specific.
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*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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* Currently only needed for cache-v6.S and cache-v7.S, see
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* __flush_icache_all for the generic implementation.
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*
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* flush_kern_all()
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*
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* Unconditionally clean and invalidate the entire cache.
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*
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* flush_user_all()
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*
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* Clean and invalidate all user space cache entries
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* before a change of page tables.
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*
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* flush_user_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address space before a change of page tables.
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* - start - user start address (inclusive, page aligned)
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* - end - user end address (exclusive, page aligned)
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* - flags - vma->vm_flags field
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*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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* - start - virtual start address
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* - end - virtual end address
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*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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* - start - virtual start address
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* - end - virtual end address
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*
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* flush_kern_dcache_area(kaddr, size)
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*
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* Ensure that the data held in page is written back.
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* - kaddr - page address
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* - size - region size
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*
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* DMA Cache Coherency
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* ===================
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*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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* - start - virtual start address
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* - end - virtual end address
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*/
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struct cpu_cache_fns {
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void (*flush_icache_all)(void);
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void (*flush_kern_all)(void);
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void (*flush_user_all)(void);
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void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
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void (*coherent_kern_range)(unsigned long, unsigned long);
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void (*coherent_user_range)(unsigned long, unsigned long);
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void (*flush_kern_dcache_area)(void *, size_t);
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void (*dma_map_area)(const void *, size_t, int);
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void (*dma_unmap_area)(const void *, size_t, int);
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void (*dma_flush_range)(const void *, const void *);
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};
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/*
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* Select the calling method
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*/
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#ifdef MULTI_CACHE
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extern struct cpu_cache_fns cpu_cache;
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#define __cpuc_flush_icache_all cpu_cache.flush_icache_all
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#define __cpuc_flush_kern_all cpu_cache.flush_kern_all
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#define __cpuc_flush_user_all cpu_cache.flush_user_all
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#define __cpuc_flush_user_range cpu_cache.flush_user_range
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#define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
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#define __cpuc_coherent_user_range cpu_cache.coherent_user_range
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#define __cpuc_flush_dcache_area cpu_cache.flush_kern_dcache_area
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/*
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* These are private to the dma-mapping API. Do not use directly.
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* Their sole purpose is to ensure that data held in the cache
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* is visible to DMA, or data written by DMA to system memory is
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* visible to the CPU.
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*/
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#define dmac_map_area cpu_cache.dma_map_area
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#define dmac_unmap_area cpu_cache.dma_unmap_area
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#define dmac_flush_range cpu_cache.dma_flush_range
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#else
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#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all)
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#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
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#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
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#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
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#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
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#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
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#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
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extern void __cpuc_flush_icache_all(void);
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extern void __cpuc_flush_kern_all(void);
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extern void __cpuc_flush_user_all(void);
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extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
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extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
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extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
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extern void __cpuc_flush_dcache_area(void *, size_t);
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/*
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* These are private to the dma-mapping API. Do not use directly.
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* Their sole purpose is to ensure that data held in the cache
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* is visible to DMA, or data written by DMA to system memory is
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* visible to the CPU.
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*/
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#define dmac_map_area __glue(_CACHE,_dma_map_area)
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#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
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#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
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extern void dmac_map_area(const void *, size_t, int);
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extern void dmac_unmap_area(const void *, size_t, int);
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extern void dmac_flush_range(const void *, const void *);
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#endif
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/*
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* Copy user data from/to a page which is mapped into a different
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* processes address space. Really, we want to allow our "user
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* space" model to handle this.
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*/
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extern void copy_to_user_page(struct vm_area_struct *, struct page *,
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unsigned long, void *, const void *, unsigned long);
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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} while (0)
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/*
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* Convert calls to our calling convention.
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*/
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/* Invalidate I-cache */
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#define __flush_icache_all_generic() \
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asm("mcr p15, 0, %0, c7, c5, 0" \
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: : "r" (0));
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/* Invalidate I-cache inner shareable */
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#define __flush_icache_all_v7_smp() \
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asm("mcr p15, 0, %0, c7, c1, 0" \
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: : "r" (0));
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/*
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* Optimized __flush_icache_all for the common cases. Note that UP ARMv7
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* will fall through to use __flush_icache_all_generic.
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*/
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#if (defined(CONFIG_CPU_V7) && defined(CONFIG_CPU_V6)) || \
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defined(CONFIG_SMP_ON_UP)
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#define __flush_icache_preferred __cpuc_flush_icache_all
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#elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
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#define __flush_icache_preferred __flush_icache_all_v7_smp
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#elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920)
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#define __flush_icache_preferred __cpuc_flush_icache_all
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#else
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#define __flush_icache_preferred __flush_icache_all_generic
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#endif
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static inline void __flush_icache_all(void)
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{
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__flush_icache_preferred();
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}
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#define flush_cache_all() __cpuc_flush_kern_all()
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static inline void vivt_flush_cache_mm(struct mm_struct *mm)
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{
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if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
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__cpuc_flush_user_all();
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}
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static inline void
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vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
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{
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if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
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__cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
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vma->vm_flags);
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}
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static inline void
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vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
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{
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if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
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unsigned long addr = user_addr & PAGE_MASK;
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__cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
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}
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}
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#ifndef CONFIG_CPU_CACHE_VIPT
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#define flush_cache_mm(mm) \
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vivt_flush_cache_mm(mm)
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#define flush_cache_range(vma,start,end) \
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vivt_flush_cache_range(vma,start,end)
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#define flush_cache_page(vma,addr,pfn) \
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vivt_flush_cache_page(vma,addr,pfn)
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#else
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extern void flush_cache_mm(struct mm_struct *mm);
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extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
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extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
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#endif
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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/*
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* flush_cache_user_range is used when we want to ensure that the
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* Harvard caches are synchronised for the user space address range.
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* This is used for the ARM private sys_cacheflush system call.
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*/
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#define flush_cache_user_range(vma,start,end) \
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__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
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/*
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* Perform necessary cache operations to ensure that data previously
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* stored within this range of addresses can be executed by the CPU.
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*/
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#define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
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/*
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* Perform necessary cache operations to ensure that the TLB will
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* see data written in the specified area.
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*/
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#define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
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/*
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* flush_dcache_page is used when the kernel has written to the page
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* cache page at virtual address page->virtual.
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*
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* If this page isn't mapped (ie, page_mapping == NULL), or it might
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* have userspace mappings, then we _must_ always clean + invalidate
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* the dcache entries associated with the kernel mapping.
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*
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* Otherwise we can defer the operation, and clean the cache when we are
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* about to change to user space. This is the same method as used on SPARC64.
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* See update_mmu_cache for the user space part.
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*/
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *);
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static inline void flush_kernel_vmap_range(void *addr, int size)
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{
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if ((cache_is_vivt() || cache_is_vipt_aliasing()))
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__cpuc_flush_dcache_area(addr, (size_t)size);
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}
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static inline void invalidate_kernel_vmap_range(void *addr, int size)
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{
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if ((cache_is_vivt() || cache_is_vipt_aliasing()))
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__cpuc_flush_dcache_area(addr, (size_t)size);
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}
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#define ARCH_HAS_FLUSH_ANON_PAGE
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static inline void flush_anon_page(struct vm_area_struct *vma,
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struct page *page, unsigned long vmaddr)
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{
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extern void __flush_anon_page(struct vm_area_struct *vma,
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struct page *, unsigned long);
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if (PageAnon(page))
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__flush_anon_page(vma, page, vmaddr);
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}
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#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
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static inline void flush_kernel_dcache_page(struct page *page)
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{
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}
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#define flush_dcache_mmap_lock(mapping) \
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spin_lock_irq(&(mapping)->tree_lock)
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#define flush_dcache_mmap_unlock(mapping) \
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spin_unlock_irq(&(mapping)->tree_lock)
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#define flush_icache_user_range(vma,page,addr,len) \
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flush_dcache_page(page)
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/*
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* We don't appear to need to do anything here. In fact, if we did, we'd
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* duplicate cache flushing elsewhere performed by flush_dcache_page().
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*/
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#define flush_icache_page(vma,page) do { } while (0)
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/*
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* flush_cache_vmap() is used when creating mappings (eg, via vmap,
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* vmalloc, ioremap etc) in kernel space for pages. On non-VIPT
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* caches, since the direct-mappings of these pages may contain cached
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* data, we need to do a full cache flush to ensure that writebacks
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* don't corrupt data placed into these pages via the new mappings.
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*/
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static inline void flush_cache_vmap(unsigned long start, unsigned long end)
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{
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if (!cache_is_vipt_nonaliasing())
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flush_cache_all();
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else
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/*
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* set_pte_at() called from vmap_pte_range() does not
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* have a DSB after cleaning the cache line.
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*/
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dsb();
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}
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static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
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{
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if (!cache_is_vipt_nonaliasing())
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flush_cache_all();
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}
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#endif
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