1d5a1a6e92
Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
278 lines
7.8 KiB
C
278 lines
7.8 KiB
C
/*
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* arch/arm/mach-orion5x/ts78xx-setup.c
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*
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* Maintainer: Alexander Clouter <alex@digriz.org.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/ata_platform.h>
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#include <linux/m48t86.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/orion5x.h>
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#include "common.h"
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#include "mpp.h"
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/*****************************************************************************
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* TS-78xx Info
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****************************************************************************/
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/*
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* FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
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*/
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#define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000
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#define TS78XX_FPGA_REGS_VIRT_BASE 0xff900000
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#define TS78XX_FPGA_REGS_SIZE SZ_1M
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#define TS78XX_FPGA_REGS_SYSCON_ID (TS78XX_FPGA_REGS_VIRT_BASE | 0x000)
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#define TS78XX_FPGA_REGS_SYSCON_LCDI (TS78XX_FPGA_REGS_VIRT_BASE | 0x004)
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#define TS78XX_FPGA_REGS_SYSCON_LCDO (TS78XX_FPGA_REGS_VIRT_BASE | 0x008)
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#define TS78XX_FPGA_REGS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x808)
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#define TS78XX_FPGA_REGS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c)
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/*
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* 512kB NOR flash Device
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*/
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#define TS78XX_NOR_BOOT_BASE 0xff800000
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#define TS78XX_NOR_BOOT_SIZE SZ_512K
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc ts78xx_io_desc[] __initdata = {
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{
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.virtual = TS78XX_FPGA_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
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.length = TS78XX_FPGA_REGS_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init ts78xx_map_io(void)
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{
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orion5x_map_io();
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iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
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}
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/*****************************************************************************
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* 512kB NOR Boot Flash - the chip is a M25P40
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****************************************************************************/
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static struct mtd_partition ts78xx_nor_boot_flash_resources[] = {
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{
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.name = "ts-bootrom",
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.offset = 0,
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/* only the first 256kB is used */
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.size = SZ_256K,
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.mask_flags = MTD_WRITEABLE,
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},
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};
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static struct physmap_flash_data ts78xx_nor_boot_flash_data = {
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.width = 1,
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.parts = ts78xx_nor_boot_flash_resources,
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.nr_parts = ARRAY_SIZE(ts78xx_nor_boot_flash_resources),
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};
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static struct resource ts78xx_nor_boot_flash_resource = {
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.flags = IORESOURCE_MEM,
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.start = TS78XX_NOR_BOOT_BASE,
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.end = TS78XX_NOR_BOOT_BASE + TS78XX_NOR_BOOT_SIZE - 1,
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};
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static struct platform_device ts78xx_nor_boot_flash = {
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.name = "physmap-flash",
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.id = -1,
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.dev = {
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.platform_data = &ts78xx_nor_boot_flash_data,
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},
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.num_resources = 1,
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.resource = &ts78xx_nor_boot_flash_resource,
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};
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/*****************************************************************************
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* Ethernet
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****************************************************************************/
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static struct mv643xx_eth_platform_data ts78xx_eth_data = {
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.phy_addr = 0,
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.force_phy_addr = 1,
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};
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/*****************************************************************************
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* RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
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****************************************************************************/
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#ifdef CONFIG_RTC_DRV_M48T86
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static unsigned char ts78xx_rtc_readbyte(unsigned long addr)
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{
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writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL);
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return readb(TS78XX_FPGA_REGS_RTC_DATA);
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}
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static void ts78xx_rtc_writebyte(unsigned char value, unsigned long addr)
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{
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writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL);
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writeb(value, TS78XX_FPGA_REGS_RTC_DATA);
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}
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static struct m48t86_ops ts78xx_rtc_ops = {
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.readbyte = ts78xx_rtc_readbyte,
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.writebyte = ts78xx_rtc_writebyte,
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};
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static struct platform_device ts78xx_rtc_device = {
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.name = "rtc-m48t86",
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.id = -1,
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.dev = {
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.platform_data = &ts78xx_rtc_ops,
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},
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.num_resources = 0,
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};
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/*
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* TS uses some of the user storage space on the RTC chip so see if it is
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* present; as it's an optional feature at purchase time and not all boards
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* will have it present
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*
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* I've used the method TS use in their rtc7800.c example for the detection
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*
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* TODO: track down a guinea pig without an RTC to see if we can work out a
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* better RTC detection routine
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*/
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static int __init ts78xx_rtc_init(void)
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{
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unsigned char tmp_rtc0, tmp_rtc1;
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tmp_rtc0 = ts78xx_rtc_readbyte(126);
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tmp_rtc1 = ts78xx_rtc_readbyte(127);
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ts78xx_rtc_writebyte(0x00, 126);
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ts78xx_rtc_writebyte(0x55, 127);
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if (ts78xx_rtc_readbyte(127) == 0x55) {
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ts78xx_rtc_writebyte(0xaa, 127);
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if (ts78xx_rtc_readbyte(127) == 0xaa
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&& ts78xx_rtc_readbyte(126) == 0x00) {
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ts78xx_rtc_writebyte(tmp_rtc0, 126);
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ts78xx_rtc_writebyte(tmp_rtc1, 127);
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platform_device_register(&ts78xx_rtc_device);
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return 1;
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}
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}
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return 0;
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};
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#else
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static int __init ts78xx_rtc_init(void)
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{
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return 0;
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}
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#endif
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/*****************************************************************************
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* SATA
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****************************************************************************/
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static struct mv_sata_platform_data ts78xx_sata_data = {
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.n_ports = 2,
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};
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/*****************************************************************************
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* print some information regarding the board
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****************************************************************************/
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static void __init ts78xx_print_board_id(void)
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{
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unsigned int board_info;
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board_info = readl(TS78XX_FPGA_REGS_SYSCON_ID);
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printk(KERN_INFO "TS-78xx Info: FPGA rev=%.2x, Board Magic=%.6x, ",
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board_info & 0xff,
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(board_info >> 8) & 0xffffff);
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board_info = readl(TS78XX_FPGA_REGS_SYSCON_LCDI);
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printk("JP1=%d, JP2=%d\n",
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(board_info >> 30) & 0x1,
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(board_info >> 31) & 0x1);
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};
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/*****************************************************************************
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* General Setup
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****************************************************************************/
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static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
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{ 0, MPP_UNUSED },
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{ 1, MPP_GPIO }, /* JTAG Clock */
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{ 2, MPP_GPIO }, /* JTAG Data In */
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{ 3, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB2B */
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{ 4, MPP_GPIO }, /* JTAG Data Out */
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{ 5, MPP_GPIO }, /* JTAG TMS */
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{ 6, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
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{ 7, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB22B */
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{ 8, MPP_UNUSED },
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{ 9, MPP_UNUSED },
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{ 10, MPP_UNUSED },
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{ 11, MPP_UNUSED },
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{ 12, MPP_UNUSED },
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{ 13, MPP_UNUSED },
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{ 14, MPP_UNUSED },
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{ 15, MPP_UNUSED },
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{ 16, MPP_UART },
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{ 17, MPP_UART },
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{ 18, MPP_UART },
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{ 19, MPP_UART },
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{ -1 },
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};
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static void __init ts78xx_init(void)
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{
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/*
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* Setup basic Orion functions. Need to be called early.
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*/
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orion5x_init();
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ts78xx_print_board_id();
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orion5x_mpp_conf(ts78xx_mpp_modes);
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/*
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* MPP[20] PCI Clock Out 1
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* MPP[21] PCI Clock Out 0
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* MPP[22] Unused
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* MPP[23] Unused
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* MPP[24] Unused
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* MPP[25] Unused
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*/
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/*
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* Configure peripherals.
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*/
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orion5x_ehci0_init();
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orion5x_ehci1_init();
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orion5x_eth_init(&ts78xx_eth_data);
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orion5x_sata_init(&ts78xx_sata_data);
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orion5x_uart0_init();
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orion5x_uart1_init();
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orion5x_xor_init();
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orion5x_setup_dev_boot_win(TS78XX_NOR_BOOT_BASE,
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TS78XX_NOR_BOOT_SIZE);
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platform_device_register(&ts78xx_nor_boot_flash);
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if (!ts78xx_rtc_init())
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printk(KERN_INFO "TS-78xx RTC not detected or enabled\n");
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}
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MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
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/* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
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.phys_io = ORION5X_REGS_PHYS_BASE,
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.io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
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.boot_params = 0x00000100,
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.init_machine = ts78xx_init,
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.map_io = ts78xx_map_io,
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.init_irq = orion5x_init_irq,
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.timer = &orion5x_timer,
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MACHINE_END
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