52142e756e
On platforms doing non-coherent DMA (4xx, 8xx, ...), it's important that the kmalloc minimum alignment is set to the cache line size, to avoid sharing cache lines between different objects, so that DMA to one of the objects doesn't corrupt the other. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
36 lines
924 B
C
36 lines
924 B
C
#ifndef _ASM_POWERPC_PAGE_32_H
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#define _ASM_POWERPC_PAGE_32_H
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#ifdef __KERNEL__
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#define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32
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#define PPC_MEMSTART 0
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#ifdef CONFIG_NOT_COHERENT_CACHE
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#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
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#endif
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#ifndef __ASSEMBLY__
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/*
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* The basic type of a PTE - 64 bits for those CPUs with > 32 bit
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* physical addressing. For now this just the IBM PPC440.
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*/
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#ifdef CONFIG_PTE_64BIT
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typedef unsigned long long pte_basic_t;
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#define PTE_SHIFT (PAGE_SHIFT - 3) /* 512 ptes per page */
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#else
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typedef unsigned long pte_basic_t;
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#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */
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#endif
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struct page;
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extern void clear_pages(void *page, int order);
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static inline void clear_page(void *page) { clear_pages(page, 0); }
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extern void copy_page(void *to, void *from);
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#include <asm-generic/page.h>
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PAGE_32_H */
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