141 lines
5.7 KiB
C
141 lines
5.7 KiB
C
/*
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* Defines for the MSP interrupt controller.
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*
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* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
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* Author: Carsten Langgaard, carstenl@mips.com
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*/
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#ifndef _MSP_SLP_INT_H
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#define _MSP_SLP_INT_H
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/*
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* The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
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* hierarchical system. The first level are the direct MIPS interrupts
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* and are assigned the interrupt range 0-7. The second level is the SLM
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* interrupt controller and is assigned the range 8-39. The third level
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* comprises the Peripherial block, the PCI block, the PCI MSI block and
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* the SLP. The PCI interrupts and the SLP errors are handled by the
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* relevant subsystems so the core interrupt code needs only concern
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* itself with the Peripheral block. These are assigned interrupts in
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* the range 40-71.
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*/
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/*
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* IRQs directly connected to CPU
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*/
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#define MSP_MIPS_INTBASE 0
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#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
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#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
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#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
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#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
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#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */
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#define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */
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#define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */
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#define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */
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/*
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* IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
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* These defines should be tied to the register definition for the SLM
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* interrupt routine. For now, just use hard-coded values.
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*/
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#define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8)
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#define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0)
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/* External interrupt 0 */
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#define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1)
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/* External interrupt 1 */
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#define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2)
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/* External interrupt 2 */
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#define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3)
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/* External interrupt 3 */
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/* Reserved 4-7 */
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/*
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*************************************************************************
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* DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
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* Some MSP produces have this interrupt labelled as Voice and some are *
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* SEC mbox ... *
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*************************************************************************
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*/
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#define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8)
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/* Cascaded IRQ for Voice Engine*/
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#define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9)
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/* TDM interrupt */
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#define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10)
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/* Cascaded IRQ for MAC 0 */
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#define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11)
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/* Cascaded IRQ for MAC 1 */
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#define MSP_INT_SEC (MSP_SLP_INTBASE + 12)
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/* IRQ for security engine */
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#define MSP_INT_PER (MSP_SLP_INTBASE + 13)
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/* Peripheral interrupt */
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#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14)
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/* SLP timer 0 */
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#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15)
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/* SLP timer 1 */
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#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16)
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/* SLP timer 2 */
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#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17)
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/* Cascaded MIPS timer */
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#define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18)
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/* Block Copy */
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#define MSP_INT_UART0 (MSP_SLP_INTBASE + 19)
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/* UART 0 */
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#define MSP_INT_PCI (MSP_SLP_INTBASE + 20)
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/* PCI subsystem */
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#define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21)
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/* PCI doorbell */
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#define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22)
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/* PCI Message Signal */
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#define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23)
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/* PCI Block Copy 0 */
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#define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24)
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/* PCI Block Copy 1 */
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#define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25)
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/* SLP error condition */
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#define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26)
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/* IRQ for MAC2 */
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/* Reserved 26-31 */
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/*
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* IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
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*/
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#define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32)
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/* Reserved 0-1 */
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#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
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/* UART 1 */
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/* Reserved 3-5 */
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#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
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/* 2-wire */
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#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
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/* Peripheral timer block out 0 */
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#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
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/* Peripheral timer block out 1 */
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/* Reserved 9 */
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#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
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/* SPI RX complete */
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#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
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/* SPI TX complete */
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#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
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/* GPIO */
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#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
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/* Peripheral error */
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/* Reserved 14-31 */
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#endif /* !_MSP_SLP_INT_H */
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