255 lines
6.5 KiB
C
255 lines
6.5 KiB
C
/*
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* Copyright (C) 1995 Linus Torvalds
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* Adapted from 'alpha' version by Gary Thomas
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* Modified by Cort Dougan (cort@cs.nmt.edu)
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* Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
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* Further modified for generic 8xx by Dan.
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*/
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/*
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* bootup setup stuff..
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/time.h>
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#include <linux/rtc.h>
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#include <linux/fsl_devices.h>
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#include <asm/io.h>
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#include <asm/mpc8xx.h>
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#include <asm/8xx_immap.h>
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#include <asm/prom.h>
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#include <asm/fs_pd.h>
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#include <mm/mmu_decl.h>
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#include <sysdev/mpc8xx_pic.h>
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#include "mpc8xx.h"
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struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
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extern int cpm_pic_init(void);
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extern int cpm_get_irq(void);
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/* A place holder for time base interrupts, if they are ever enabled. */
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static irqreturn_t timebase_interrupt(int irq, void *dev)
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{
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printk ("timebase_interrupt()\n");
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return IRQ_HANDLED;
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}
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static struct irqaction tbint_irqaction = {
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.handler = timebase_interrupt,
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.name = "tbint",
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};
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/* per-board overridable init_internal_rtc() function. */
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void __init __attribute__ ((weak))
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init_internal_rtc(void)
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{
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sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
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/* Disable the RTC one second and alarm interrupts. */
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clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
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/* Enable the RTC */
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setbits16(&sys_tmr->sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
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immr_unmap(sys_tmr);
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}
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static int __init get_freq(char *name, unsigned long *val)
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{
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struct device_node *cpu;
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const unsigned int *fp;
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int found = 0;
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/* The cpu node should have timebase and clock frequency properties */
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cpu = of_find_node_by_type(NULL, "cpu");
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if (cpu) {
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fp = of_get_property(cpu, name, NULL);
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if (fp) {
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found = 1;
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*val = *fp;
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}
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of_node_put(cpu);
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}
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return found;
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}
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/* The decrementer counts at the system (internal) clock frequency divided by
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* sixteen, or external oscillator divided by four. We force the processor
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* to use system clock divided by sixteen.
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*/
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void __init mpc8xx_calibrate_decr(void)
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{
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struct device_node *cpu;
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cark8xx_t __iomem *clk_r1;
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car8xx_t __iomem *clk_r2;
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sitk8xx_t __iomem *sys_tmr1;
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sit8xx_t __iomem *sys_tmr2;
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int irq, virq;
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clk_r1 = immr_map(im_clkrstk);
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/* Unlock the SCCR. */
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out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
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out_be32(&clk_r1->cark_sccrk, KAPWR_KEY);
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immr_unmap(clk_r1);
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/* Force all 8xx processors to use divide by 16 processor clock. */
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clk_r2 = immr_map(im_clkrst);
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setbits32(&clk_r2->car_sccr, 0x02000000);
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immr_unmap(clk_r2);
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/* Processor frequency is MHz.
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*/
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ppc_proc_freq = 50000000;
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if (!get_freq("clock-frequency", &ppc_proc_freq))
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printk(KERN_ERR "WARNING: Estimating processor frequency "
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"(not found)\n");
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ppc_tb_freq = ppc_proc_freq / 16;
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printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
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/* Perform some more timer/timebase initialization. This used
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* to be done elsewhere, but other changes caused it to get
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* called more than once....that is a bad thing.
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*
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* First, unlock all of the registers we are going to modify.
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* To protect them from corruption during power down, registers
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* that are maintained by keep alive power are "locked". To
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* modify these registers we have to write the key value to
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* the key location associated with the register.
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* Some boards power up with these unlocked, while others
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* are locked. Writing anything (including the unlock code?)
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* to the unlocked registers will lock them again. So, here
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* we guarantee the registers are locked, then we unlock them
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* for our use.
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*/
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sys_tmr1 = immr_map(im_sitk);
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out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
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out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
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out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
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out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY);
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out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY);
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out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY);
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immr_unmap(sys_tmr1);
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init_internal_rtc();
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/* Enabling the decrementer also enables the timebase interrupts
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* (or from the other point of view, to get decrementer interrupts
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* we have to enable the timebase). The decrementer interrupt
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* is wired into the vector table, nothing to do here for that.
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*/
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cpu = of_find_node_by_type(NULL, "cpu");
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virq= irq_of_parse_and_map(cpu, 0);
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irq = irq_map[virq].hwirq;
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sys_tmr2 = immr_map(im_sit);
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out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
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(TBSCR_TBF | TBSCR_TBE));
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immr_unmap(sys_tmr2);
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if (setup_irq(virq, &tbint_irqaction))
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panic("Could not allocate timer IRQ!");
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}
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/* The RTC on the MPC8xx is an internal register.
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* We want to protect this during power down, so we need to unlock,
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* modify, and re-lock.
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*/
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int mpc8xx_set_rtc_time(struct rtc_time *tm)
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{
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sitk8xx_t __iomem *sys_tmr1;
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sit8xx_t __iomem *sys_tmr2;
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int time;
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sys_tmr1 = immr_map(im_sitk);
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sys_tmr2 = immr_map(im_sit);
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time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday,
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tm->tm_hour, tm->tm_min, tm->tm_sec);
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out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY);
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out_be32(&sys_tmr2->sit_rtc, time);
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out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY);
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immr_unmap(sys_tmr2);
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immr_unmap(sys_tmr1);
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return 0;
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}
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void mpc8xx_get_rtc_time(struct rtc_time *tm)
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{
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unsigned long data;
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sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
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/* Get time from the RTC. */
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data = in_be32(&sys_tmr->sit_rtc);
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to_tm(data, tm);
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tm->tm_year -= 1900;
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tm->tm_mon -= 1;
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immr_unmap(sys_tmr);
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return;
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}
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void mpc8xx_restart(char *cmd)
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{
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car8xx_t __iomem *clk_r = immr_map(im_clkrst);
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local_irq_disable();
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setbits32(&clk_r->car_plprcr, 0x00000080);
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/* Clear the ME bit in MSR to cause checkstop on machine check
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*/
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mtmsr(mfmsr() & ~0x1000);
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in_8(&clk_r->res[0]);
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panic("Restart failed\n");
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}
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static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_chip *chip;
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int cascade_irq;
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if ((cascade_irq = cpm_get_irq()) >= 0) {
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struct irq_desc *cdesc = irq_to_desc(cascade_irq);
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generic_handle_irq(cascade_irq);
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chip = irq_desc_get_chip(cdesc);
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chip->irq_eoi(&cdesc->irq_data);
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}
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chip = irq_desc_get_chip(desc);
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chip->irq_eoi(&desc->irq_data);
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}
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/* Initialize the internal interrupt controllers. The number of
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* interrupts supported can vary with the processor type, and the
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* 82xx family can have up to 64.
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* External interrupts can be either edge or level triggered, and
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* need to be initialized by the appropriate driver.
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*/
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void __init mpc8xx_pics_init(void)
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{
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int irq;
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if (mpc8xx_pic_init()) {
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printk(KERN_ERR "Failed interrupt 8xx controller initialization\n");
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return;
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}
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irq = cpm_pic_init();
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if (irq != NO_IRQ)
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irq_set_chained_handler(irq, cpm_cascade);
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}
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