3d6e48f433
When running a 31-bit ptrace, on either an s390 or s390x kernel, reads and writes into a padding area in struct user_regs_struct32 will result in a kernel panic. This is also known as CVE-2008-1514. Test case available here: http://sources.redhat.com/cgi-bin/cvsweb.cgi/~checkout~/tests/ptrace-tests/tests/user-area-padding.c?cvsroot=systemtap Steps to reproduce: 1) wget the above 2) gcc -o user-area-padding-31bit user-area-padding.c -Wall -ggdb2 -D_GNU_SOURCE -m31 3) ./user-area-padding-31bit <panic> Test status ----------- Without patch, both s390 and s390x kernels panic. With patch, the test case, as well as the gdb testsuite, pass without incident, padding area reads returning zero, writes ignored. Nb: original version returned -EINVAL on write attempts, which broke the gdb test and made the test case slightly unhappy, Jan Kratochvil suggested the change to return 0 on write attempts. Signed-off-by: Jarod Wilson <jarod@redhat.com> Tested-by: Jan Kratochvil <jan.kratochvil@redhat.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
84 lines
2.4 KiB
C
84 lines
2.4 KiB
C
#ifndef _PTRACE32_H
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#define _PTRACE32_H
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#include "compat_linux.h" /* needed for psw_compat_t */
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typedef struct {
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__u32 cr[3];
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} per_cr_words32;
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typedef struct {
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__u16 perc_atmid; /* 0x096 */
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__u32 address; /* 0x098 */
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__u8 access_id; /* 0x0a1 */
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} per_lowcore_words32;
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typedef struct {
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union {
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per_cr_words32 words;
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} control_regs;
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/*
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* Use these flags instead of setting em_instruction_fetch
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* directly they are used so that single stepping can be
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* switched on & off while not affecting other tracing
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*/
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unsigned single_step : 1;
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unsigned instruction_fetch : 1;
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unsigned : 30;
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/*
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* These addresses are copied into cr10 & cr11 if single
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* stepping is switched off
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*/
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__u32 starting_addr;
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__u32 ending_addr;
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union {
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per_lowcore_words32 words;
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} lowcore;
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} per_struct32;
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struct user_regs_struct32
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{
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psw_compat_t psw;
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u32 gprs[NUM_GPRS];
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u32 acrs[NUM_ACRS];
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u32 orig_gpr2;
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/* nb: there's a 4-byte hole here */
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s390_fp_regs fp_regs;
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/*
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* These per registers are in here so that gdb can modify them
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* itself as there is no "official" ptrace interface for hardware
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* watchpoints. This is the way intel does it.
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*/
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per_struct32 per_info;
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u32 ieee_instruction_pointer;
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/* Used to give failing instruction back to user for ieee exceptions */
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};
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struct user32 {
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/* We start with the registers, to mimic the way that "memory"
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is returned from the ptrace(3,...) function. */
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struct user_regs_struct32 regs; /* Where the registers are actually stored */
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/* The rest of this junk is to help gdb figure out what goes where */
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u32 u_tsize; /* Text segment size (pages). */
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u32 u_dsize; /* Data segment size (pages). */
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u32 u_ssize; /* Stack segment size (pages). */
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u32 start_code; /* Starting virtual address of text. */
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u32 start_stack; /* Starting virtual address of stack area.
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This is actually the bottom of the stack,
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the top of the stack is always found in the
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esp register. */
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s32 signal; /* Signal that caused the core dump. */
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u32 u_ar0; /* Used by gdb to help find the values for */
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/* the registers. */
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u32 magic; /* To uniquely identify a core file */
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char u_comm[32]; /* User command that was responsible */
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};
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typedef struct
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{
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__u32 len;
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__u32 kernel_addr;
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__u32 process_addr;
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} ptrace_area_emu31;
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#endif /* _PTRACE32_H */
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